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riscv: add medeleg unit tests
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Adds basic unit tests for the `medeleg` register.
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rmsyn committed Oct 27, 2024
1 parent 90139e2 commit 08b6b0e
Showing 1 changed file with 38 additions and 0 deletions.
38 changes: 38 additions & 0 deletions riscv/src/register/medeleg.rs
Original file line number Diff line number Diff line change
Expand Up @@ -126,3 +126,41 @@ set_clear_csr!(
set_clear_csr!(
/// Store/AMO Page Fault Delegate
, set_store_page_fault, clear_store_page_fault, 1 << 15);

#[cfg(test)]
mod tests {
use super::*;

macro_rules! test_field {
($reg:ident, $field:ident) => {{
$crate::paste! {
assert!(!$reg.$field());

$reg.[<set_ $field>](true);
assert!($reg.$field());

$reg.[<set_ $field>](false);
assert!(!$reg.$field());
}
}};
}

#[test]
fn test_medeleg() {
let mut m = Medeleg::from_bits(0);

test_field!(m, instruction_misaligned);
test_field!(m, instruction_fault);
test_field!(m, illegal_instruction);
test_field!(m, breakpoint);
test_field!(m, load_misaligned);
test_field!(m, load_fault);
test_field!(m, store_misaligned);
test_field!(m, store_fault);
test_field!(m, user_env_call);
test_field!(m, supervisor_env_call);
test_field!(m, instruction_page_fault);
test_field!(m, load_page_fault);
test_field!(m, store_page_fault);
}
}

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