Removing user mode registers

rust-embedded · Sep 21, 2023 · 2d31842 · 2d31842
1 parent ee80fd4
commit 2d31842
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Showing 17 changed files with 26 additions and 361 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -32,6 +32,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Fix `scause::Exception` missing `SupervisorEnvCall`
 - Removed user-level interrupts from `mcause::Interrupt` and `scause::Interrupt`
 - Removed user-level interrupts from `mstatus`
+- Removed machine environment call delegation from `medeleg`
+- Removed user-level interrupts from machine and supervisor mode interrupt-related registers.
+
+### Removed
+
+- User mode registers removed, as they are no longer supported in RISC-V
 
 ## [v0.10.1] - 2023-01-18
 

diff --git a/src/register.rs b/src/register.rs
@@ -14,18 +14,6 @@
 #[macro_use]
 mod macros;
 
-// User Trap Setup
-pub mod uie;
-pub mod ustatus;
-pub mod utvec;
-
-// User Trap Handling
-pub mod ucause;
-pub mod uepc;
-pub mod uip;
-pub mod uscratch;
-pub mod utval;
-
 // User Floating-Point CSRs
 // TODO: frm, fflags
 pub mod fcsr;

diff --git a/src/register/medeleg.rs b/src/register/medeleg.rs
@@ -73,12 +73,6 @@ impl Medeleg {
         self.bits & (1 << 9) != 0
     }
 
-    /// Environment Call from M-mode Delegate
-    #[inline]
-    pub fn machine_env_call(&self) -> bool {
-        self.bits & (1 << 11) != 0
-    }
-
     /// Instruction Page Fault Delegate
     #[inline]
     pub fn instruction_page_fault(&self) -> bool {
@@ -132,9 +126,6 @@ set_clear_csr!(
 set_clear_csr!(
     /// Environment Call from S-mode Delegate
     , set_supervisor_env_call, clear_supervisor_env_call, 1 << 9);
-set_clear_csr!(
-    /// Environment Call from M-mode Delegate
-    , set_machine_env_call, clear_machine_env_call, 1 << 11);
 set_clear_csr!(
     /// Instruction Page Fault Delegate
     , set_instruction_page_fault, clear_instruction_page_fault, 1 << 12);

diff --git a/src/register/mideleg.rs b/src/register/mideleg.rs
@@ -13,36 +13,18 @@ impl Mideleg {
         self.bits
     }
 
-    /// User Software Interrupt Delegate
-    #[inline]
-    pub fn usoft(&self) -> bool {
-        self.bits & (1 << 0) != 0
-    }
-
     /// Supervisor Software Interrupt Delegate
     #[inline]
     pub fn ssoft(&self) -> bool {
         self.bits & (1 << 1) != 0
     }
 
-    /// User Timer Interrupt Delegate
-    #[inline]
-    pub fn utimer(&self) -> bool {
-        self.bits & (1 << 4) != 0
-    }
-
     /// Supervisor Timer Interrupt Delegate
     #[inline]
     pub fn stimer(&self) -> bool {
         self.bits & (1 << 5) != 0
     }
 
-    /// User External Interrupt Delegate
-    #[inline]
-    pub fn uext(&self) -> bool {
-        self.bits & (1 << 8) != 0
-    }
-
     /// Supervisor External Interrupt Delegate
     #[inline]
     pub fn sext(&self) -> bool {
@@ -54,21 +36,12 @@ read_csr_as!(Mideleg, 0x303);
 set!(0x303);
 clear!(0x303);
 
-set_clear_csr!(
-    /// User Software Interrupt Delegate
-    , set_usoft, clear_usoft, 1 << 0);
 set_clear_csr!(
     /// Supervisor Software Interrupt Delegate
     , set_ssoft, clear_ssoft, 1 << 1);
-set_clear_csr!(
-    /// User Timer Interrupt Delegate
-    , set_utimer, clear_utimer, 1 << 4);
 set_clear_csr!(
     /// Supervisor Timer Interrupt Delegate
     , set_stimer, clear_stimer, 1 << 5);
-set_clear_csr!(
-    /// User External Interrupt Delegate
-    , set_uext, clear_uext, 1 << 8);
 set_clear_csr!(
     /// Supervisor External Interrupt Delegate
     , set_sext, clear_sext, 1 << 9);
diff --git a/src/register/mie.rs b/src/register/mie.rs
@@ -13,12 +13,6 @@ impl Mie {
         self.bits
     }
 
-    /// User Software Interrupt Enable
-    #[inline]
-    pub fn usoft(&self) -> bool {
-        self.bits & (1 << 0) != 0
-    }
-
     /// Supervisor Software Interrupt Enable
     #[inline]
     pub fn ssoft(&self) -> bool {
@@ -31,12 +25,6 @@ impl Mie {
         self.bits & (1 << 3) != 0
     }
 
-    /// User Timer Interrupt Enable
-    #[inline]
-    pub fn utimer(&self) -> bool {
-        self.bits & (1 << 4) != 0
-    }
-
     /// Supervisor Timer Interrupt Enable
     #[inline]
     pub fn stimer(&self) -> bool {
@@ -49,12 +37,6 @@ impl Mie {
         self.bits & (1 << 7) != 0
     }
 
-    /// User External Interrupt Enable
-    #[inline]
-    pub fn uext(&self) -> bool {
-        self.bits & (1 << 8) != 0
-    }
-
     /// Supervisor External Interrupt Enable
     #[inline]
     pub fn sext(&self) -> bool {
@@ -72,27 +54,18 @@ read_csr_as!(Mie, 0x304);
 set!(0x304);
 clear!(0x304);
 
-set_clear_csr!(
-    /// User Software Interrupt Enable
-    , set_usoft, clear_usoft, 1 << 0);
 set_clear_csr!(
     /// Supervisor Software Interrupt Enable
     , set_ssoft, clear_ssoft, 1 << 1);
 set_clear_csr!(
     /// Machine Software Interrupt Enable
     , set_msoft, clear_msoft, 1 << 3);
-set_clear_csr!(
-    /// User Timer Interrupt Enable
-    , set_utimer, clear_utimer, 1 << 4);
 set_clear_csr!(
     /// Supervisor Timer Interrupt Enable
     , set_stimer, clear_stimer, 1 << 5);
 set_clear_csr!(
     /// Machine Timer Interrupt Enable
     , set_mtimer, clear_mtimer, 1 << 7);
-set_clear_csr!(
-    /// User External Interrupt Enable
-    , set_uext, clear_uext, 1 << 8);
 set_clear_csr!(
     /// Supervisor External Interrupt Enable
     , set_sext, clear_sext, 1 << 9);

diff --git a/src/register/mip.rs b/src/register/mip.rs
@@ -13,12 +13,6 @@ impl Mip {
         self.bits
     }
 
-    /// User Software Interrupt Pending
-    #[inline]
-    pub fn usoft(&self) -> bool {
-        self.bits & (1 << 0) != 0
-    }
-
     /// Supervisor Software Interrupt Pending
     #[inline]
     pub fn ssoft(&self) -> bool {
@@ -31,12 +25,6 @@ impl Mip {
         self.bits & (1 << 3) != 0
     }
 
-    /// User Timer Interrupt Pending
-    #[inline]
-    pub fn utimer(&self) -> bool {
-        self.bits & (1 << 4) != 0
-    }
-
     /// Supervisor Timer Interrupt Pending
     #[inline]
     pub fn stimer(&self) -> bool {
@@ -49,12 +37,6 @@ impl Mip {
         self.bits & (1 << 7) != 0
     }
 
-    /// User External Interrupt Pending
-    #[inline]
-    pub fn uext(&self) -> bool {
-        self.bits & (1 << 8) != 0
-    }
-
     /// Supervisor External Interrupt Pending
     #[inline]
     pub fn sext(&self) -> bool {
@@ -72,21 +54,12 @@ read_csr_as!(Mip, 0x344);
 set!(0x344);
 clear!(0x344);
 
-set_clear_csr!(
-    /// User Software Interrupt Pending
-    , set_usoft, clear_usoft, 1 << 0);
 set_clear_csr!(
     /// Supervisor Software Interrupt Pending
     , set_ssoft, clear_ssoft, 1 << 1);
-set_clear_csr!(
-    /// User Timer Interrupt Pending
-    , set_utimer, clear_utimer, 1 << 4);
 set_clear_csr!(
     /// Supervisor Timer Interrupt Pending
     , set_stimer, clear_stimer, 1 << 5);
-set_clear_csr!(
-    /// User External Interrupt Pending
-    , set_uext, clear_uext, 1 << 8);
 set_clear_csr!(
     /// Supervisor External Interrupt Pending
     , set_sext, clear_sext, 1 << 9);
diff --git a/src/register/sie.rs b/src/register/sie.rs
@@ -13,36 +13,18 @@ impl Sie {
         self.bits
     }
 
-    /// User Software Interrupt Enable
-    #[inline]
-    pub fn usoft(&self) -> bool {
-        self.bits & (1 << 0) != 0
-    }
-
     /// Supervisor Software Interrupt Enable
     #[inline]
     pub fn ssoft(&self) -> bool {
         self.bits & (1 << 1) != 0
     }
 
-    /// User Timer Interrupt Enable
-    #[inline]
-    pub fn utimer(&self) -> bool {
-        self.bits & (1 << 4) != 0
-    }
-
     /// Supervisor Timer Interrupt Enable
     #[inline]
     pub fn stimer(&self) -> bool {
         self.bits & (1 << 5) != 0
     }
 
-    /// User External Interrupt Enable
-    #[inline]
-    pub fn uext(&self) -> bool {
-        self.bits & (1 << 8) != 0
-    }
-
     /// Supervisor External Interrupt Enable
     #[inline]
     pub fn sext(&self) -> bool {
@@ -54,21 +36,12 @@ read_csr_as!(Sie, 0x104);
 set!(0x104);
 clear!(0x104);
 
-set_clear_csr!(
-    /// User Software Interrupt Enable
-    , set_usoft, clear_usoft, 1 << 0);
 set_clear_csr!(
     /// Supervisor Software Interrupt Enable
     , set_ssoft, clear_ssoft, 1 << 1);
-set_clear_csr!(
-    /// User Timer Interrupt Enable
-    , set_utimer, clear_utimer, 1 << 4);
 set_clear_csr!(
     /// Supervisor Timer Interrupt Enable
     , set_stimer, clear_stimer, 1 << 5);
-set_clear_csr!(
-    /// User External Interrupt Enable
-    , set_uext, clear_uext, 1 << 8);
 set_clear_csr!(
     /// Supervisor External Interrupt Enable
     , set_sext, clear_sext, 1 << 9);
diff --git a/src/register/sip.rs b/src/register/sip.rs
@@ -13,36 +13,18 @@ impl Sip {
         self.bits
     }
 
-    /// User Software Interrupt Pending
-    #[inline]
-    pub fn usoft(&self) -> bool {
-        self.bits & (1 << 0) != 0
-    }
-
     /// Supervisor Software Interrupt Pending
     #[inline]
     pub fn ssoft(&self) -> bool {
         self.bits & (1 << 1) != 0
     }
 
-    /// User Timer Interrupt Pending
-    #[inline]
-    pub fn utimer(&self) -> bool {
-        self.bits & (1 << 4) != 0
-    }
-
     /// Supervisor Timer Interrupt Pending
     #[inline]
     pub fn stimer(&self) -> bool {
         self.bits & (1 << 5) != 0
     }
 
-    /// User External Interrupt Pending
-    #[inline]
-    pub fn uext(&self) -> bool {
-        self.bits & (1 << 8) != 0
-    }
-
     /// Supervisor External Interrupt Pending
     #[inline]
     pub fn sext(&self) -> bool {
@@ -51,3 +33,9 @@ impl Sip {
 }
 
 read_csr_as!(Sip, 0x144);
+set!(0x344);
+clear!(0x104);
+
+set_clear_csr!(
+    /// Supervisor Software Interrupt Pending
+    , set_ssoft, clear_ssoft, 1 << 1);
diff --git a/src/register/sstatus.rs b/src/register/sstatus.rs
@@ -1,5 +1,6 @@
 //! sstatus register
 
+pub use super::misa::XLEN;
 pub use super::mstatus::FS;
 
 /// Supervisor Status Register
@@ -16,24 +17,12 @@ pub enum SPP {
 }
 
 impl Sstatus {
-    /// User Interrupt Enable
-    #[inline]
-    pub fn uie(&self) -> bool {
-        self.bits & (1 << 0) != 0
-    }
-
     /// Supervisor Interrupt Enable
     #[inline]
     pub fn sie(&self) -> bool {
         self.bits & (1 << 1) != 0
     }
 
-    /// User Previous Interrupt Enable
-    #[inline]
-    pub fn upie(&self) -> bool {
-        self.bits & (1 << 4) != 0
-    }
-
     /// Supervisor Previous Interrupt Enable
     #[inline]
     pub fn spie(&self) -> bool {
@@ -88,6 +77,19 @@ impl Sstatus {
         self.bits & (1 << 19) != 0
     }
 
+    /// Effective xlen in U-mode (i.e., `UXLEN`).
+    ///
+    /// In RISCV-32, UXL does not exist, and `UXLEN` is always [`XLEN::XLEN32`].
+    #[inline]
+    pub fn uxl(&self) -> XLEN {
+        match () {
+            #[cfg(riscv32)]
+            () => XLEN::XLEN32,
+            #[cfg(not(riscv32))]
+            () => XLEN::from((self.bits >> 32) as u8 & 0x3),
+        }
+    }
+
     /// Whether either the FS field or XS field
     /// signals the presence of some dirty state
     #[inline]