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mstatus: use update_ for names
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And add a clarifying doc comment that this is an operation on Mstatus
values, not on the CSR itself.
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jsgf committed May 7, 2024
1 parent c269cbd commit 37581f1
Showing 1 changed file with 102 additions and 41 deletions.
143 changes: 102 additions & 41 deletions riscv/src/register/mstatus.rs
Original file line number Diff line number Diff line change
Expand Up @@ -93,9 +93,12 @@ impl Mstatus {
self.bits & (1 << 1) != 0
}

/// Set Supervisor Interrupt Enable
/// Update Supervisor Interrupt Enable
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_sie`]/[`clear_sie`] to directly update the CSR.
#[inline]
pub fn set_sie(&self, sie: bool) -> Self {
pub fn update_sie(&self, sie: bool) -> Self {
self.bf_insert(1, 1, sie as usize)
}

Expand All @@ -105,9 +108,12 @@ impl Mstatus {
self.bits & (1 << 3) != 0
}

/// Set Machine Interrupt Enable
/// Update Machine Interrupt Enable
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_mie`]/[`clear_mie`] to directly update the CSR.
#[inline]
pub fn set_mie(&self, mie: bool) -> Self {
pub fn update_mie(&self, mie: bool) -> Self {
self.bf_insert(3, 1, mie as usize)
}

Expand All @@ -117,9 +123,12 @@ impl Mstatus {
self.bits & (1 << 5) != 0
}

/// Supervisor Previous Interrupt Enable
/// Updateervisor Previous Interrupt Enable
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_spie`]` to directly update the CSR.
#[inline]
pub fn set_spie(&self, spie: bool) -> Self {
pub fn update_spie(&self, spie: bool) -> Self {
self.bf_insert(5, 1, spie as usize)
}

Expand All @@ -129,9 +138,12 @@ impl Mstatus {
Endianness::from(self.bits & (1 << 6) != 0)
}

/// Set U-mode non-instruction-fetch memory endianness
/// Update U-mode non-instruction-fetch memory endianness
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_ube`] to directly update the CSR.
#[inline]
pub fn set_ube(&self, endianness: Endianness) -> Self {
pub fn update_ube(&self, endianness: Endianness) -> Self {
self.bf_insert(6, 1, endianness as usize)
}

Expand All @@ -141,9 +153,12 @@ impl Mstatus {
self.bits & (1 << 7) != 0
}

/// Set Machine Previous Interrupt Enable
/// Update Machine Previous Interrupt Enable
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_mpie`] to directly update the CSR.
#[inline]
pub fn set_mpie(&self, mpie: bool) -> Self {
pub fn update_mpie(&self, mpie: bool) -> Self {
self.bf_insert(7, 1, mpie as usize)
}

Expand All @@ -156,9 +171,12 @@ impl Mstatus {
}
}

/// Set Supervisor Previous Privilege Mode
/// Update Supervisor Previous Privilege Mode
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_spp`] to directly update the CSR.
#[inline]
pub fn set_spp(&self, spp: SPP) -> Self {
pub fn update_spp(&self, spp: SPP) -> Self {
self.bf_insert(8, 1, spp as usize)
}

Expand All @@ -174,9 +192,12 @@ impl Mstatus {
}
}

/// Set Machine Previous Privilege Mode
/// Update Machine Previous Privilege Mode
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_mpp`] to directly update the CSR.
#[inline]
pub fn set_mpp(&self, mpp: MPP) -> Self {
pub fn update_mpp(&self, mpp: MPP) -> Self {
self.bf_insert(11, 2, mpp as usize)
}

Expand All @@ -196,9 +217,12 @@ impl Mstatus {
}
}

/// Set Floating-point extension state
/// Update Floating-point extension state
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_fs`] to directly update the CSR.
#[inline]
pub fn set_fs(&self, fs: FS) -> Self {
pub fn update_fs(&self, fs: FS) -> Self {
self.bf_insert(13, 2, fs as usize)
}

Expand All @@ -217,9 +241,12 @@ impl Mstatus {
}
}

/// Set Additional extension state
/// Update Additional extension state
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself.
#[inline]
pub fn set_xs(&self, xs: XS) -> Self {
pub fn update_xs(&self, xs: XS) -> Self {
self.bf_insert(15, 2, xs as usize)
}

Expand All @@ -229,9 +256,12 @@ impl Mstatus {
self.bits & (1 << 17) != 0
}

/// Set Modify Memory PRiVilege
/// Update Modify Memory PRiVilege
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_mprv`]/[`clear_mprv`] to directly update the CSR.
#[inline]
pub fn set_mprv(&self, mprv: bool) -> Self {
pub fn update_mprv(&self, mprv: bool) -> Self {
self.bf_insert(17, 1, mprv as usize)
}

Expand All @@ -241,9 +271,12 @@ impl Mstatus {
self.bits & (1 << 18) != 0
}

/// Set Permit Supervisor User Memory access
/// Update Permit Supervisor User Memory access
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_sum`]/[`clear_sum`] to directly update the CSR.
#[inline]
pub fn set_sum(&self, sum: bool) -> Self {
pub fn update_sum(&self, sum: bool) -> Self {
self.bf_insert(18, 1, sum as usize)
}

Expand All @@ -253,9 +286,12 @@ impl Mstatus {
self.bits & (1 << 19) != 0
}

/// Set Make eXecutable Readable
/// Update Make eXecutable Readable
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_mxr`]/[`clear_mxr`] to directly update the CSR.
#[inline]
pub fn set_mxr(&self, mxr: bool) -> Self {
pub fn update_mxr(&self, mxr: bool) -> Self {
self.bf_insert(19, 1, mxr as usize)
}

Expand All @@ -270,9 +306,12 @@ impl Mstatus {
self.bits & (1 << 20) != 0
}

/// Set Trap Virtual Memory
/// Update Trap Virtual Memory
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_tvm`]/[`clear_tvm`] to directly update the CSR.
#[inline]
pub fn set_tvm(&self, tvm: bool) -> Self {
pub fn update_tvm(&self, tvm: bool) -> Self {
self.bf_insert(20, 1, tvm as usize)
}

Expand All @@ -290,9 +329,12 @@ impl Mstatus {
self.bits & (1 << 21) != 0
}

/// Set Timeout Wait
/// Update Timeout Wait
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_tw`]/[`clear_tw`] to directly update the CSR.
#[inline]
pub fn set_tw(&self, tw: bool) -> Self {
pub fn update_tw(&self, tw: bool) -> Self {
self.bf_insert(21, 1, tw as usize)
}

Expand All @@ -307,9 +349,12 @@ impl Mstatus {
self.bits & (1 << 22) != 0
}

/// Set Trap SRET
/// Update Trap SRET
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_tsr`]/[`clear_tsr`] to directly update the CSR.
#[inline]
pub fn set_tsr(&self, tsr: bool) -> Self {
pub fn update_tsr(&self, tsr: bool) -> Self {
self.bf_insert(22, 1, tsr as usize)
}

Expand All @@ -326,9 +371,12 @@ impl Mstatus {
}
}

/// Set Effective xlen in U-mode (i.e., `UXLEN`).
/// Update Effective xlen in U-mode (i.e., `UXLEN`).
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself.
#[inline]
pub fn set_uxl(&self, uxl: XLEN) -> Self {
pub fn update_uxl(&self, uxl: XLEN) -> Self {
#[cfg(riscv32)]
{
*self
Expand All @@ -350,9 +398,12 @@ impl Mstatus {
}
}

/// Set Effective xlen in S-mode (i.e., `SXLEN`).
/// Update Effective xlen in S-mode (i.e., `SXLEN`).
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself.
#[inline]
pub fn set_sxl(&self, sxl: XLEN) -> Self {
pub fn update_sxl(&self, sxl: XLEN) -> Self {
#[cfg(riscv32)]
{
*self
Expand All @@ -373,9 +424,12 @@ impl Mstatus {
}
}

/// Set S-mode non-instruction-fetch memory endianness
/// Update S-mode non-instruction-fetch memory endianness
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_sbe`] to directly update the CSR.
#[inline]
pub fn set_sbe(&self, endianness: Endianness) -> Self {
pub fn update_sbe(&self, endianness: Endianness) -> Self {
#[cfg(riscv32)]
{
*self
Expand All @@ -395,9 +449,12 @@ impl Mstatus {
() => Endianness::from(self.bits & (1 << 37) != 0),
}
}

/// Set M-mode non-instruction-fetch memory endianness
pub fn set_mbe(&self, endianness: Endianness) -> Self {
/// Update M-mode non-instruction-fetch memory endianness
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself. See [`set_mbe`] to directly update the CSR.
#[inline]
pub fn update_mbe(&self, endianness: Endianness) -> Self {
#[cfg(riscv32)]
{
*self
Expand All @@ -412,9 +469,13 @@ impl Mstatus {
self.bits & (1 << (usize::BITS as usize - 1)) != 0
}

/// Set whether either the FS field or XS field signals the presence of some dirty state
/// Update whether either the FS field or XS field signals the presence of
/// some dirty state
///
/// Note this updates the [`Mstatus`] value, but does not affect the mstatus
/// CSR itself.
#[inline]
pub fn set_sd(&self, sd: bool) -> Self {
pub fn update_sd(&self, sd: bool) -> Self {
self.bf_insert(usize::BITS as usize - 1, 1, sd as usize)
}
}
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