Replace if with conditional compilation

- Replace fmvp.d.x usage with fcvt.d.w as it does not require zfa

riscv-rt/src/lib.rs

@@ -524,16 +524,14 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
         core::arch::asm!("fscsr x0"); // Zero out fcsr register csrrw x0, fcsr, x0
 
         // Zero out floating point registers
-        if cfg!(all(target_arch = "riscv32", riscvd)) {
-            // rv32 targets with double precision floating point can use fmvp.d.x
-            // to combine 2 32 bit registers to fill the 64 bit floating point
-            // register
-            riscv_rt_macros::loop_asm!("fmvp.d.x f{}, x0, x0", 32);
-        } else if cfg!(riscvd) {
-            riscv_rt_macros::loop_asm!("fmv.d.x f{}, x0", 32);
-        } else {
-            riscv_rt_macros::loop_asm!("fmv.w.x f{}, x0", 32);
-        }
+        #[cfg(all(target_arch = "riscv32", riscvd))]
+        riscv_rt_macros::loop_asm!("fcvt.d.w f{}, x0", 32);
+
+        #[cfg(all(target_arch = "riscv64", riscvd))]
+        riscv_rt_macros::loop_asm!("fmv.d.x f{}, x0", 32);
+
+        #[cfg(not(riscvd))]
+        riscv_rt_macros::loop_asm!("fmv.w.x f{}, x0", 32);
     }
 
     _setup_interrupts();