riscv: fix target architecture condition compilation

Uses a conditional compilation selector set by modern compiler versions for code gated behind a target architecture.
rust-embedded · May 3, 2024 · 7d70619 · 7d70619
1 parent a9d3e33
commit 7d70619
Showing 1 changed file with 22 additions and 22 deletions.
diff --git a/riscv/src/register/macros.rs b/riscv/src/register/macros.rs
@@ -10,14 +10,14 @@ macro_rules! read_csr {
         #[inline]
         unsafe fn _read() -> usize {
             match () {
-                #[cfg(riscv)]
+                #[cfg(target_arch = "riscv64")]
                 () => {
                     let r: usize;
                     core::arch::asm!(concat!("csrrs {0}, ", stringify!($csr_number), ", x0"), out(reg) r);
                     r
                 }
 
-                #[cfg(not(riscv))]
+                #[cfg(not(target_arch = "riscv64"))]
                 () => unimplemented!(),
             }
         }
@@ -36,14 +36,14 @@ macro_rules! read_csr_rv32 {
         #[inline]
         unsafe fn _read() -> usize {
             match () {
-                #[cfg(riscv32)]
+                #[cfg(target_arch = "riscv32")]
                 () => {
                     let r: usize;
                     core::arch::asm!(concat!("csrrs {0}, ", stringify!($csr_number), ", x0"), out(reg) r);
                     r
                 }
 
-                #[cfg(not(riscv32))]
+                #[cfg(not(target_arch = "riscv32"))]
                 () => unimplemented!(),
             }
         }
@@ -127,10 +127,10 @@ macro_rules! write_csr {
         #[allow(unused_variables)]
         unsafe fn _write(bits: usize) {
             match () {
-                #[cfg(riscv)]
+                #[cfg(target_arch = "riscv64")]
                 () => core::arch::asm!(concat!("csrrw x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
-                #[cfg(not(riscv))]
+                #[cfg(not(target_arch = "riscv64"))]
                 () => unimplemented!(),
             }
         }
@@ -150,10 +150,10 @@ macro_rules! write_csr_rv32 {
         #[allow(unused_variables)]
         unsafe fn _write(bits: usize) {
             match () {
-                #[cfg(riscv32)]
+                #[cfg(target_arch = "riscv32")]
                 () => core::arch::asm!(concat!("csrrw x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
-                #[cfg(not(riscv32))]
+                #[cfg(not(target_arch = "riscv32"))]
                 () => unimplemented!(),
             }
         }
@@ -199,10 +199,10 @@ macro_rules! set {
         #[allow(unused_variables)]
         unsafe fn _set(bits: usize) {
             match () {
-                #[cfg(riscv)]
+                #[cfg(target_arch = "riscv64")]
                 () => core::arch::asm!(concat!("csrrs x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
-                #[cfg(not(riscv))]
+                #[cfg(not(target_arch = "riscv64"))]
                 () => unimplemented!(),
             }
         }
@@ -220,10 +220,10 @@ macro_rules! set_rv32 {
         #[allow(unused_variables)]
         unsafe fn _set(bits: usize) {
             match () {
-                #[cfg(riscv32)]
+                #[cfg(target_arch = "riscv32")]
                 () => core::arch::asm!(concat!("csrrs x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
-                #[cfg(not(riscv32))]
+                #[cfg(not(target_arch = "riscv32"))]
                 () => unimplemented!(),
             }
         }
@@ -241,10 +241,10 @@ macro_rules! clear {
         #[allow(unused_variables)]
         unsafe fn _clear(bits: usize) {
             match () {
-                #[cfg(riscv)]
+                #[cfg(target_arch = "riscv64")]
                 () => core::arch::asm!(concat!("csrrc x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
-                #[cfg(not(riscv))]
+                #[cfg(not(target_arch = "riscv64"))]
                 () => unimplemented!(),
             }
         }
@@ -262,10 +262,10 @@ macro_rules! clear_rv32 {
         #[allow(unused_variables)]
         unsafe fn _clear(bits: usize) {
             match () {
-                #[cfg(riscv32)]
+                #[cfg(target_arch = "riscv32")]
                 () => core::arch::asm!(concat!("csrrc x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
-                #[cfg(not(riscv32))]
+                #[cfg(not(target_arch = "riscv32"))]
                 () => unimplemented!(),
             }
         }
@@ -316,7 +316,7 @@ macro_rules! read_composite_csr {
         #[inline]
         pub fn read64() -> u64 {
             match () {
-                #[cfg(riscv32)]
+                #[cfg(target_arch = "riscv32")]
                 () => loop {
                     let hi = $hi;
                     let lo = $lo;
@@ -325,7 +325,7 @@ macro_rules! read_composite_csr {
                     }
                 },
 
-                #[cfg(not(riscv32))]
+                #[cfg(not(target_arch = "riscv32"))]
                 () => $lo as u64,
             }
         }
@@ -337,10 +337,10 @@ macro_rules! set_pmp {
         /// Set the pmp configuration corresponding to the index
         #[inline]
         pub unsafe fn set_pmp(index: usize, range: Range, permission: Permission, locked: bool) {
-            #[cfg(riscv32)]
+            #[cfg(target_arch = "riscv32")]
             assert!(index < 4);
 
-            #[cfg(riscv64)]
+            #[cfg(target_arch = "riscv64")]
             assert!(index < 8);
 
             let mut value = _read();
@@ -357,10 +357,10 @@ macro_rules! clear_pmp {
         /// Clear the pmp configuration corresponding to the index
         #[inline]
         pub unsafe fn clear_pmp(index: usize) {
-            #[cfg(riscv32)]
+            #[cfg(target_arch = "riscv32")]
             assert!(index < 4);
 
-            #[cfg(riscv64)]
+            #[cfg(target_arch = "riscv64")]
             assert!(index < 8);
 
             let mut value = _read();