Merge pull request #150 from rust-embedded/remove-fcsr

Transition to cargo workspace
rust-embedded · Nov 17, 2023 · 8071b55 · 8071b55
2 parents 4ab67d6 + c92affa
commit 8071b55
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Showing 55 changed files with 44 additions and 29 deletions.
diff --git a/.github/workflows/changelog.yaml b/.github/workflows/changelog.yaml
@@ -1,4 +1,4 @@
-name: Check CHANGELOG.md
+name: Changelog check
 
 on:
   merge_group:
@@ -12,9 +12,18 @@ jobs:
       - name: Checkout code
         uses: actions/checkout@v4
 
-      - name: Check for CHANGELOG.md
+      - name: Check which component is modified 
+        uses: dorny/paths-filter@v2
+        id: changes
+        with:
+          filters: |
+            riscv:
+              - 'riscv/**'
+
+      - name: Check for CHANGELOG.md (riscv)
+        if: steps.changes.outputs.riscv == 'true'
         uses: dangoslen/changelog-enforcer@v3
         with:
+          changeLogPath: ./riscv/CHANGELOG.md
           skipLabels: 'skip changelog'
-          missingUpdateErrorMessage: 'Please add a changelog entry in the CHANGELOG.md file.'
-
+          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.'
diff --git a/Cargo.toml b/Cargo.toml
@@ -1,26 +1,5 @@
-[package]
-name = "riscv"
-version = "0.10.1"
-edition = "2021"
-rust-version = "1.59"
-repository = "https://github.com/rust-embedded/riscv"
-authors = ["The RISC-V Team <[email protected]>"]
-categories = ["embedded", "hardware-support", "no-std"]
-description = "Low level access to RISC-V processors"
-keywords = ["riscv", "register", "peripheral"]
-license = "ISC"
-
-[package.metadata.docs.rs]
-all-features = true
-default-target = "riscv64imac-unknown-none-elf"
-targets = [
-    "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
-    "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
+[workspace]
+resolver = "2"
+members = [
+    "riscv",
 ]
-
-[features]
-critical-section-single-hart = ["critical-section/restore-state-bool"]
-
-[dependencies]
-critical-section = "1.1.2"
-embedded-hal = "1.0.0-rc.1"
diff --git a/CHANGELOG.md → riscv/CHANGELOG.md b/CHANGELOG.md → riscv/CHANGELOG.md
@@ -20,6 +20,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Transitioning to cargo workspace
 - Update `embedded-hal` dependency to v1.0 (bumps MSRV to 1.60)
 - `misa::MXL` renamed to `misa::XLEN`
 - Removed `bit_field` dependency

diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml
@@ -0,0 +1,26 @@
+[package]
+name = "riscv"
+version = "0.10.1"
+edition = "2021"
+rust-version = "1.59"
+repository = "https://github.com/rust-embedded/riscv"
+authors = ["The RISC-V Team <[email protected]>"]
+categories = ["embedded", "hardware-support", "no-std"]
+description = "Low level access to RISC-V processors"
+keywords = ["riscv", "register", "peripheral"]
+license = "ISC"
+
+[package.metadata.docs.rs]
+all-features = true
+default-target = "riscv64imac-unknown-none-elf"
+targets = [
+    "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
+    "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
+]
+
+[features]
+critical-section-single-hart = ["critical-section/restore-state-bool"]
+
+[dependencies]
+critical-section = "1.1.2"
+embedded-hal = "1.0.0-rc.1"
diff --git a/build.rs → riscv/build.rs b/build.rs → riscv/build.rs
diff --git a/src/asm.rs → riscv/src/asm.rs b/src/asm.rs → riscv/src/asm.rs
diff --git a/src/critical_section.rs → riscv/src/critical_section.rs b/src/critical_section.rs → riscv/src/critical_section.rs
diff --git a/src/delay.rs → riscv/src/delay.rs b/src/delay.rs → riscv/src/delay.rs
diff --git a/src/interrupt.rs → riscv/src/interrupt.rs b/src/interrupt.rs → riscv/src/interrupt.rs
diff --git a/src/lib.rs → riscv/src/lib.rs b/src/lib.rs → riscv/src/lib.rs
diff --git a/src/macros.rs → riscv/src/macros.rs b/src/macros.rs → riscv/src/macros.rs
diff --git a/src/register.rs → riscv/src/register.rs b/src/register.rs → riscv/src/register.rs
diff --git a/src/register/cycle.rs → riscv/src/register/cycle.rs b/src/register/cycle.rs → riscv/src/register/cycle.rs
diff --git a/src/register/cycleh.rs → riscv/src/register/cycleh.rs b/src/register/cycleh.rs → riscv/src/register/cycleh.rs
diff --git a/src/register/hpmcounterx.rs → riscv/src/register/hpmcounterx.rs b/src/register/hpmcounterx.rs → riscv/src/register/hpmcounterx.rs
diff --git a/src/register/instret.rs → riscv/src/register/instret.rs b/src/register/instret.rs → riscv/src/register/instret.rs
diff --git a/src/register/instreth.rs → riscv/src/register/instreth.rs b/src/register/instreth.rs → riscv/src/register/instreth.rs
diff --git a/src/register/macros.rs → riscv/src/register/macros.rs b/src/register/macros.rs → riscv/src/register/macros.rs
diff --git a/src/register/marchid.rs → riscv/src/register/marchid.rs b/src/register/marchid.rs → riscv/src/register/marchid.rs
diff --git a/src/register/mcause.rs → riscv/src/register/mcause.rs b/src/register/mcause.rs → riscv/src/register/mcause.rs
diff --git a/src/register/mcounteren.rs → riscv/src/register/mcounteren.rs b/src/register/mcounteren.rs → riscv/src/register/mcounteren.rs
diff --git a/src/register/mcycle.rs → riscv/src/register/mcycle.rs b/src/register/mcycle.rs → riscv/src/register/mcycle.rs
diff --git a/src/register/mcycleh.rs → riscv/src/register/mcycleh.rs b/src/register/mcycleh.rs → riscv/src/register/mcycleh.rs
diff --git a/src/register/medeleg.rs → riscv/src/register/medeleg.rs b/src/register/medeleg.rs → riscv/src/register/medeleg.rs
diff --git a/src/register/mepc.rs → riscv/src/register/mepc.rs b/src/register/mepc.rs → riscv/src/register/mepc.rs
diff --git a/src/register/mhartid.rs → riscv/src/register/mhartid.rs b/src/register/mhartid.rs → riscv/src/register/mhartid.rs
diff --git a/src/register/mhpmcounterx.rs → riscv/src/register/mhpmcounterx.rs b/src/register/mhpmcounterx.rs → riscv/src/register/mhpmcounterx.rs
diff --git a/src/register/mhpmeventx.rs → riscv/src/register/mhpmeventx.rs b/src/register/mhpmeventx.rs → riscv/src/register/mhpmeventx.rs
diff --git a/src/register/mideleg.rs → riscv/src/register/mideleg.rs b/src/register/mideleg.rs → riscv/src/register/mideleg.rs
diff --git a/src/register/mie.rs → riscv/src/register/mie.rs b/src/register/mie.rs → riscv/src/register/mie.rs
diff --git a/src/register/mimpid.rs → riscv/src/register/mimpid.rs b/src/register/mimpid.rs → riscv/src/register/mimpid.rs
diff --git a/src/register/minstret.rs → riscv/src/register/minstret.rs b/src/register/minstret.rs → riscv/src/register/minstret.rs
diff --git a/src/register/minstreth.rs → riscv/src/register/minstreth.rs b/src/register/minstreth.rs → riscv/src/register/minstreth.rs
diff --git a/src/register/mip.rs → riscv/src/register/mip.rs b/src/register/mip.rs → riscv/src/register/mip.rs
diff --git a/src/register/misa.rs → riscv/src/register/misa.rs b/src/register/misa.rs → riscv/src/register/misa.rs
diff --git a/src/register/mscratch.rs → riscv/src/register/mscratch.rs b/src/register/mscratch.rs → riscv/src/register/mscratch.rs
diff --git a/src/register/mstatus.rs → riscv/src/register/mstatus.rs b/src/register/mstatus.rs → riscv/src/register/mstatus.rs
diff --git a/src/register/mstatush.rs → riscv/src/register/mstatush.rs b/src/register/mstatush.rs → riscv/src/register/mstatush.rs
diff --git a/src/register/mtval.rs → riscv/src/register/mtval.rs b/src/register/mtval.rs → riscv/src/register/mtval.rs
diff --git a/src/register/mtvec.rs → riscv/src/register/mtvec.rs b/src/register/mtvec.rs → riscv/src/register/mtvec.rs
diff --git a/src/register/mvendorid.rs → riscv/src/register/mvendorid.rs b/src/register/mvendorid.rs → riscv/src/register/mvendorid.rs
diff --git a/src/register/pmpaddrx.rs → riscv/src/register/pmpaddrx.rs b/src/register/pmpaddrx.rs → riscv/src/register/pmpaddrx.rs
diff --git a/src/register/pmpcfgx.rs → riscv/src/register/pmpcfgx.rs b/src/register/pmpcfgx.rs → riscv/src/register/pmpcfgx.rs
diff --git a/src/register/satp.rs → riscv/src/register/satp.rs b/src/register/satp.rs → riscv/src/register/satp.rs
diff --git a/src/register/scause.rs → riscv/src/register/scause.rs b/src/register/scause.rs → riscv/src/register/scause.rs
diff --git a/src/register/scounteren.rs → riscv/src/register/scounteren.rs b/src/register/scounteren.rs → riscv/src/register/scounteren.rs
diff --git a/src/register/sepc.rs → riscv/src/register/sepc.rs b/src/register/sepc.rs → riscv/src/register/sepc.rs
diff --git a/src/register/sie.rs → riscv/src/register/sie.rs b/src/register/sie.rs → riscv/src/register/sie.rs
diff --git a/src/register/sip.rs → riscv/src/register/sip.rs b/src/register/sip.rs → riscv/src/register/sip.rs
diff --git a/src/register/sscratch.rs → riscv/src/register/sscratch.rs b/src/register/sscratch.rs → riscv/src/register/sscratch.rs
diff --git a/src/register/sstatus.rs → riscv/src/register/sstatus.rs b/src/register/sstatus.rs → riscv/src/register/sstatus.rs
diff --git a/src/register/stval.rs → riscv/src/register/stval.rs b/src/register/stval.rs → riscv/src/register/stval.rs
diff --git a/src/register/stvec.rs → riscv/src/register/stvec.rs b/src/register/stvec.rs → riscv/src/register/stvec.rs
diff --git a/src/register/time.rs → riscv/src/register/time.rs b/src/register/time.rs → riscv/src/register/time.rs
diff --git a/src/register/timeh.rs → riscv/src/register/timeh.rs b/src/register/timeh.rs → riscv/src/register/timeh.rs