fix for riscv64

rust-embedded · Sep 20, 2023 · 93c1911 · 93c1911
1 parent 438b062
commit 93c1911
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/register/mstatus.rs b/src/register/mstatus.rs
@@ -210,7 +210,7 @@ impl Mstatus {
             #[cfg(riscv32)]
             () => XLEN::XLEN32,
             #[cfg(not(riscv32))]
-            () => XLEN::from((self.bits() >> 32) as u8 & 0x3),
+            () => XLEN::from((self.bits >> 32) as u8 & 0x3),
         }
     }
 
@@ -223,7 +223,7 @@ impl Mstatus {
             #[cfg(riscv32)]
             () => XLEN::XLEN32,
             #[cfg(not(riscv32))]
-            () => XLEN::from((self.bits() >> 34) as u8 & 0x3),
+            () => XLEN::from((self.bits >> 34) as u8 & 0x3),
         }
     }