Merge pull request #219 from rmsyn/riscv/csr-macro

riscv: add CSR-defining macros

riscv/CHANGELOG.md

@@ -25,6 +25,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Add `Mstatus` vector extension support
 - Add fallible counterparts to all functions that `panic`
 - Add `riscv-pac` as a dependency
+- Add CSR-defining macros to create in-memory types
 
 ### Fixed
 

riscv/Cargo.toml

@@ -29,3 +29,4 @@ critical-section = "1.1.2"
 embedded-hal = "1.0.0"
 riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
 riscv-macros = { path = "macros", version = "0.1.0", optional = true }
+paste = "1.0.15"

riscv/src/lib.rs

@@ -35,8 +35,10 @@
 #![no_std]
 #![allow(clippy::missing_safety_doc)]
 
+pub use paste::paste;
+
 pub mod asm;
-pub(crate) mod bits;
+pub mod bits;
 pub mod delay;
 pub mod interrupt;
 pub mod register;

riscv/src/register.rs

@@ -107,6 +107,9 @@ pub mod minstreth;
 mod mhpmeventx;
 pub use self::mhpmeventx::*;
 
+#[cfg(test)]
+mod tests;
+
 // TODO: Debug/Trace Registers (shared with Debug Mode)
 
 // TODO: Debug Mode Registers