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adjust the workspace
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romancardenas committed Dec 28, 2023
1 parent b5a6c0b commit e70afe4
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22 changes: 16 additions & 6 deletions .github/workflows/changelog.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -19,10 +19,12 @@ jobs:
filters: |
riscv:
- 'riscv/**'
riscv-rt:
- 'riscv-rt/**'
riscv-pac:
- 'riscv-pac/**'
riscv-rt:
- 'riscv-rt/**'
riscv-semihosting:
- 'riscv-semihosting/**'
- name: Check for CHANGELOG.md (riscv)
if: steps.changes.outputs.riscv == 'true'
Expand All @@ -32,6 +34,14 @@ jobs:
skipLabels: 'skip changelog'
missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.'

- name: Check for CHANGELOG.md (riscv-pac)
if: steps.changes.outputs.riscv-pac == 'true'
uses: dangoslen/changelog-enforcer@v3
with:
changeLogPath: ./riscv-pac/CHANGELOG.md
skipLabels: 'skip changelog'
missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-pac/CHANGELOG.md file.'

- name: Check for CHANGELOG.md (riscv-rt)
if: steps.changes.outputs.riscv-rt == 'true'
uses: dangoslen/changelog-enforcer@v3
Expand All @@ -40,10 +50,10 @@ jobs:
skipLabels: 'skip changelog'
missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-rt/CHANGELOG.md file.'

- name: Check for CHANGELOG.md (riscv-pac)
if: steps.changes.outputs.riscv-pac == 'true'
- name: Check for CHANGELOG.md (riscv-semihosting)
if: steps.changes.outputs.riscv-semihosting == 'true'
uses: dangoslen/changelog-enforcer@v3
with:
changeLogPath: ./riscv-pac/CHANGELOG.md
changeLogPath: ./riscv-semihosting/CHANGELOG.md
skipLabels: 'skip changelog'
missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-pac/CHANGELOG.md file.'
missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-semihosting/CHANGELOG.md file.'
46 changes: 46 additions & 0 deletions .github/workflows/riscv-semihosting.yaml
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@@ -0,0 +1,46 @@
on:
push:
branches: [ master, semihosting ]
pull_request:
merge_group:

name: Build check (riscv-semihosting)

jobs:
# We check that the crate builds and links for all the toolchains and targets.
build-riscv:
strategy:
matrix:
# All generated code should be running on stable now, MRSV is 1.60.0
toolchain: [ stable, nightly, 1.60.0 ]
target:
- riscv32i-unknown-none-elf
- riscv32imc-unknown-none-elf
- riscv32imac-unknown-none-elf
- riscv64imac-unknown-none-elf
- riscv64gc-unknown-none-elf
include:
# Nightly is only for reference and allowed to fail
- toolchain: nightly
experimental: true
runs-on: ubuntu-latest
continue-on-error: ${{ matrix.experimental || false }}
steps:
- uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@master
with:
toolchain: ${{ matrix.toolchain }}
targets: ${{ matrix.target }}
- name: Build (M-mode)
run: cargo build --package riscv-semihosting --target ${{ matrix.target }} --features machine-mode
- name: Build (U-mode)
run: cargo build --package riscv-semihosting --target ${{ matrix.target }} --features=user-mode

# Job to check that all the builds succeeded
build-check:
needs:
- build-riscv
runs-on: ubuntu-latest
if: always()
steps:
- run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'
1 change: 1 addition & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -4,4 +4,5 @@ members = [
"riscv",
"riscv-pac",
"riscv-rt",
"riscv-semihosting",
]
4 changes: 3 additions & 1 deletion README.md
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Expand Up @@ -5,7 +5,7 @@ This repository contains various crates useful for writing Rust programs on RISC
* [`riscv`]: CPU registers access and intrinsics
* [`riscv-pac`]: Common traits to be implemented by RISC-V PACs
* [`riscv-rt`]: Startup code and interrupt handling

* [`riscv-semihosting`]: Semihosting for RISC-V processors

This project is developed and maintained by the [RISC-V team][team].

Expand All @@ -22,6 +22,8 @@ Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
to intervene to uphold that code of conduct.

[`riscv`]: https://crates.io/crates/riscv
[`riscv-pac`]: https://crates.io/crates/riscv-pac
[`riscv-rt`]: https://crates.io/crates/riscv-rt
[`riscv-semihosting`]: https://crates.io/crates/riscv-semihosting
[team]: https://github.com/rust-embedded/wg#the-risc-v-team
[CoC]: CODE_OF_CONDUCT.md
31 changes: 0 additions & 31 deletions riscv-semihosting/.github/workflows/check.yml

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21 changes: 0 additions & 21 deletions riscv-semihosting/.github/workflows/doc.yml

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18 changes: 0 additions & 18 deletions riscv-semihosting/.github/workflows/fmt.yml

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2 changes: 0 additions & 2 deletions riscv-semihosting/.gitignore

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1 change: 1 addition & 0 deletions riscv-semihosting/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ This project adheres to [Semantic Versioning](http://semver.org/).

## [Unreleased]

- Moved to the `riscv` Cargo workspace
- Bring in API changes from
[cortex-m-semihosting](https://github.com/rust-embedded/cortex-m/tree/master/cortex-m-semihosting),
including:
Expand Down
4 changes: 2 additions & 2 deletions riscv-semihosting/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -11,10 +11,10 @@ categories = ["no-std", "embedded"]
license = "MIT OR Apache-2.0"
name = "riscv-semihosting"
readme = "README.md"
repository = "https://github.com/riscv-rust/riscv-semihosting"
repository = "https://github.com/riscv-rust/riscv"
version = "0.0.1"
edition = "2021"
rust-version = "1.59.0"
rust-version = "1.60.0"

[features]
default = ["jlink-quirks"]
Expand Down
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