riscv: add mie unit tests

Adds basic unit tests for the `mie` register.
rust-embedded · Nov 5, 2024 · f5eef5b · f5eef5b
1 parent d235173
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diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
@@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use CSR helper macros to define `medeleg` register
 - Use CSR helper macros to define `mideleg` register
 - Use CSR helper macros to define `mcounteren` register
+- Use CSR helper macros to define `mie` register
 
 ## [v0.12.1] - 2024-10-20
 

diff --git a/riscv/src/register/mie.rs b/riscv/src/register/mie.rs
@@ -63,3 +63,20 @@ set_clear_csr!(
 set_clear_csr!(
     /// Machine External Interrupt Enable
     , set_mext, clear_mext, 1 << 11);
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mie() {
+        let mut m = Mie::from_bits(0);
+
+        test_csr_field!(m, ssoft);
+        test_csr_field!(m, msoft);
+        test_csr_field!(m, stimer);
+        test_csr_field!(m, mtimer);
+        test_csr_field!(m, sext);
+        test_csr_field!(m, mext);
+    }
+}