HACK(RVE): use a5 instead of t3 for RAM init

RVE does not support registers x16--x31, including t3 (x28). I replaced the use of t3 in the flash algorithm with a5 (x15) to make it compile.
rust-embedded · Feb 27, 2024 · feebe40 · feebe40
1 parent dd47e2d
commit feebe40
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
@@ -165,9 +165,9 @@ cfg_global_asm!(
     bgeu t0, t2, 2f
 1:  ",
     #[cfg(target_arch = "riscv32")]
-    "lw t3, 0(t1)
+    "lw a5, 0(t1)
     addi t1, t1, 4
-    sw t3, 0(t0)
+    sw a5, 0(t0)
     addi t0, t0, 4
     bltu t0, t2, 1b",
     #[cfg(target_arch = "riscv64")]