Rework of mcause and scause registers #139
Merged
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I did a rework of
mcause
andscause
registers to follow the latest RISC-V specification. Namely, I removed the user-level interrupt sources and fixed a missing exception type inscause
.I also used the
From
andTryFrom
traits, so now theInterrupt
andException
enumerations are more usable. I plan to re-export these enums inriscv-rt
to avoid code duplicates and simplify a bit the logic of the runtime.