Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Rework of mcause and scause registers #139

Merged
merged 3 commits into from
Aug 11, 2023
Merged

Conversation

romancardenas
Copy link
Contributor

I did a rework of mcause and scause registers to follow the latest RISC-V specification. Namely, I removed the user-level interrupt sources and fixed a missing exception type in scause.

I also used the From and TryFrom traits, so now the Interrupt and Exception enumerations are more usable. I plan to re-export these enums in riscv-rt to avoid code duplicates and simplify a bit the logic of the runtime.

@romancardenas romancardenas requested a review from a team as a code owner August 11, 2023 14:34
Copy link
Contributor

@almindor almindor left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM, thanks!

@almindor almindor added this pull request to the merge queue Aug 11, 2023
Merged via the queue into master with commit 622f6fe Aug 11, 2023
43 checks passed
@romancardenas romancardenas deleted the interrupts-exceptions branch August 14, 2023 22:33
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants