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riscv-rt: remove riscv-target ;riscv:update for embedded-hal to 1.0.0-rc.2 #160

Merged
merged 12 commits into from
Dec 4, 2023
6 changes: 3 additions & 3 deletions .github/workflows/riscv-rt.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,8 @@ jobs:
build:
strategy:
matrix:
# All generated code should be running on stable now, MRSV is 1.59.0
toolchain: [ stable, nightly, 1.59.0 ]
# All generated code should be running on stable now, MRSV is 1.60.0
toolchain: [ stable, nightly, 1.60.0 ]
target:
- riscv32i-unknown-none-elf
- riscv32imc-unknown-none-elf
Expand Down Expand Up @@ -41,7 +41,7 @@ jobs:
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=single-hart
- name: Build example (all features)
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features

# Job to check that all the builds succeeded
build-check:
needs:
Expand Down
6 changes: 3 additions & 3 deletions .github/workflows/riscv.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ jobs:
build-riscv:
strategy:
matrix:
# All generated code should be running on stable now, MRSV is 1.59.0
# All generated code should be running on stable now, MRSV is 1.60.0
toolchain: [ stable, nightly, 1.60.0 ]
target:
- riscv32i-unknown-none-elf
Expand All @@ -35,7 +35,7 @@ jobs:
run: cargo build --package riscv --target ${{ matrix.target }}
- name: Build (all features)
run: cargo build --package riscv --target ${{ matrix.target }} --all-features

# On MacOS, Ubuntu, and Windows, we at least make sure that the crate builds and links.
build-others:
strategy:
Expand All @@ -49,7 +49,7 @@ jobs:
run: cargo build --package riscv
- name: Build (all features)
run: cargo build --package riscv --all-features

# Job to check that all the builds succeeded
build-check:
needs:
Expand Down
2 changes: 2 additions & 0 deletions riscv-rt/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

### Changed

- Removed riscv-target dependency for build
- Upgrade rust-version to 1.60
- Cargo workspace for riscv and riscv-rt
- Use inline assembly instead of pre-compiled blobs
- Removed bors in favor of GitHub Merge Queue
Expand Down
5 changes: 1 addition & 4 deletions riscv-rt/Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
[package]
name = "riscv-rt"
version = "0.11.0"
rust-version = "1.59"
rust-version = "1.60"
repository = "https://github.com/rust-embedded/riscv"
authors = ["The RISC-V Team <[email protected]>"]
categories = ["embedded", "no-std"]
Expand All @@ -21,6 +21,3 @@ riscv-rt-macros = { path = "macros", version = "0.2.0" }

[dev-dependencies]
panic-halt = "0.2.0"

[build-dependencies]
riscv-target = "0.1.2"
2 changes: 1 addition & 1 deletion riscv-rt/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team].

## Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.59 and up. It *might*
This crate is guaranteed to compile on stable Rust 1.60 and up. It *might*
compile with older versions but that may change in any new patch release.

## License
Expand Down
43 changes: 36 additions & 7 deletions riscv-rt/build.rs
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
// NOTE: Adapted from cortex-m/build.rs

use riscv_target::Target;
use std::{env, fs, io, path::PathBuf};
use std::{collections::HashSet, env, fs, io, path::PathBuf};

fn add_linker_script(arch_width: u32) -> io::Result<()> {
// Read the file to a string and replace all occurrences of ${ARCH_WIDTH} with the arch width
Expand All @@ -18,17 +17,47 @@ fn add_linker_script(arch_width: u32) -> io::Result<()> {
Ok(())
}

/// Parse the target RISC-V architecture and returns its bit width and the extension set
fn parse_target(target: &str) -> (u32, HashSet<char>) {
// isolate bit width and extensions from the rest of the target information
let arch = target
.trim_start_matches("riscv")
.split('-')
.next()
.unwrap();

let bits = arch
.chars()
.take_while(|c| c.is_ascii_digit())
.collect::<String>()
.parse::<u32>()
.unwrap();

let mut extensions: HashSet<char> = arch.chars().skip_while(|c| c.is_ascii_digit()).collect();
// get rid of the 'g' shorthand extension
if extensions.remove(&'g') {
extensions.insert('i');
extensions.insert('m');
extensions.insert('a');
extensions.insert('f');
extensions.insert('d');
}

(bits, extensions)
}

fn main() {
let target = env::var("TARGET").unwrap();
let _name = env::var("CARGO_PKG_NAME").unwrap();

// set configuration flags depending on the target
if target.starts_with("riscv") {
println!("cargo:rustc-cfg=riscv");
let target = Target::from_target_str(&target);

// generate the linker script
let arch_width = match target.bits {
let (bits, extensions) = parse_target(&target);

// generate the linker script and expose the ISA width
let arch_width = match bits {
32 => {
println!("cargo:rustc-cfg=riscv32");
4
Expand All @@ -42,8 +71,8 @@ fn main() {
add_linker_script(arch_width).unwrap();

// expose the ISA extensions
if target.has_extension('m') {
println!("cargo:rustc-cfg=riscvm");
for ext in &extensions {
println!("cargo:rustc-cfg=riscv{}", ext);
}
}
}
6 changes: 3 additions & 3 deletions riscv-rt/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
//!
//! # Minimum Supported Rust Version (MSRV)
//!
//! This crate is guaranteed to compile on stable Rust 1.59 and up. It *might*
//! This crate is guaranteed to compile on stable Rust 1.60 and up. It *might*
//! compile with older versions but that may change in any new patch release.
//!
//! # Features
Expand Down Expand Up @@ -483,14 +483,14 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
sd {a},0({start})
addi {start},{start},8
bltu {start},{end},1b

2: // .data zero registers
li {a},0
li {input},0

la {start},_sbss
la {end},_ebss

bgeu {start},{end},4f

3: // .bss main loop
Expand Down
2 changes: 1 addition & 1 deletion riscv/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
### Changed

- Cargo workspace for riscv and riscv-rt
- Update `embedded-hal` dependency to v1.0 (bumps MSRV to 1.60)
- Update `embedded-hal` dependency to v1.0.0-rc.2 (bumps MSRV to 1.60)
- `misa::MXL` renamed to `misa::XLEN`
- Removed `bit_field` dependency
- CI actions updated. They now use `checkout@v3` and `dtolnay/rust-toolchain`.
Expand Down
4 changes: 2 additions & 2 deletions riscv/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
name = "riscv"
version = "0.10.1"
edition = "2021"
rust-version = "1.59"
rust-version = "1.60"
repository = "https://github.com/rust-embedded/riscv"
authors = ["The RISC-V Team <[email protected]>"]
categories = ["embedded", "hardware-support", "no-std"]
Expand All @@ -24,4 +24,4 @@ critical-section-single-hart = ["critical-section/restore-state-bool"]

[dependencies]
critical-section = "1.1.2"
embedded-hal = "1.0.0-rc.1"
embedded-hal = "1.0.0-rc.2"
10 changes: 5 additions & 5 deletions riscv/src/delay.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
//! Delay devices and providers
use crate::register::mcycle;
use embedded_hal::delay::DelayUs;
use embedded_hal::delay::DelayNs;

/// Machine mode cycle counter (`mcycle`) as a delay provider
#[derive(Copy, Clone)]
Expand All @@ -19,12 +19,12 @@ impl McycleDelay {
}
}

impl DelayUs for McycleDelay {
impl DelayNs for McycleDelay {
#[inline]
fn delay_us(&mut self, us: u32) {
fn delay_ns(&mut self, ns: u32) {
let t0 = mcycle::read64();
let us_64: u64 = us.into();
let clock = (us_64 * (self.ticks_second as u64)) / 1_000_000u64;
let ns_64: u64 = ns.into();
let clock = (ns_64 * (self.ticks_second as u64)) / 1_000_000_000u64;
while mcycle::read64().wrapping_sub(t0) <= clock {}
}
}
2 changes: 1 addition & 1 deletion riscv/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
//!
//! # Minimum Supported Rust Version (MSRV)
//!
//! This crate is guaranteed to compile on stable Rust 1.59 and up. It *might*
//! This crate is guaranteed to compile on stable Rust 1.60 and up. It *might*
//! compile with older versions but that may change in any new patch release.
//!
//! # Features
Expand Down