riscv-rt: Support for vectored mode interrupt handling

.github/workflows/riscv-rt.yaml

@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, riscv-rt-asm ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
@@ -39,6 +39,8 @@ jobs:
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=s-mode
       - name : Build (single-hart)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=single-hart
+      - name : Build (v-trap)
+        run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=v-trap
       - name: Build (all features)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features
 

riscv-rt/CHANGELOG.md

@@ -10,13 +10,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - Add `pre_init_trap` to detect early errors during the boot process.
+- Add `v-trap` feature to enable interrupt handling in vectored mode.
+- Add `interrupt` proc macro to help defining interrupt handlers.
+If `v-trap` feature is enabled, this macro also generates its corresponding trap.
 
 ### Changed
 
 - Moved all the assembly code to `asm.rs`
 - Use `weak` symbols for functions such as `_mp_hook` or `_start_trap`
 - `abort` is now `weak`, so it is possible to link third-party libraries including this symbol.
 - Made `cfg` variable selection more robust for custom targets
+- `_start_trap_rust` now only deals with exceptions. When an interrupt is detected, it now calls
+to `_dispatch_interrupt`.
 
 ### Removed
 

riscv-rt/Cargo.toml

@@ -12,13 +12,14 @@ license = "ISC"
 edition = "2021"
 links = "riscv-rt" # Prevent multiple versions of riscv-rt being linked
 
-[features]
-s-mode = []
-single-hart = []
-
 [dependencies]
 riscv = {path = "../riscv", version = "0.11.1"}
 riscv-rt-macros = { path = "macros", version = "0.2.1" }
 
 [dev-dependencies]
 panic-halt = "0.2.0"
+
+[features]
+s-mode = ["riscv-rt-macros/s-mode"]
+single-hart = []
+v-trap = ["riscv-rt-macros/v-trap"]

riscv-rt/examples/empty.rs

@@ -4,10 +4,16 @@
 extern crate panic_halt;
 extern crate riscv_rt;
 
-use riscv_rt::entry;
+use riscv_rt::{entry, interrupt};
 
 #[entry]
 fn main() -> ! {
     // do something here
     loop {}
 }
+
+#[interrupt]
+fn MachineSoft() {
+    // do something here
+    loop {}
+}

riscv-rt/link.x.in

@@ -28,6 +28,28 @@ PROVIDE(_max_hart_id = 0);
 PROVIDE(_hart_stack_size = 2K);
 PROVIDE(_heap_size = 0);
 
+/** TRAP ENTRY POINTS **/
+
+/* Default trap entry point. The riscv-rt crate provides a weak alias of this function,
+   which saves caller saved registers, calls _start_trap_rust, restores caller saved registers
+   and then returns. Users can override this alias by defining the symbol themselves */
+EXTERN(_start_trap);
+
+/* Default interrupt trap entry point. When vectored trap mode is enabled,
+   the riscv-rt crate provides an implementation of this function, which saves caller saved
+   registers, calls the the DefaultHandler ISR, restores caller saved registers and returns. */
+PROVIDE(_start_DefaultHandler_trap = _start_trap);
+
+/* When vectored trap mode is enabled, each interrupt source must implement its own
+   trap entry point. By default, all interrupts start in _start_trap. However, users can
+   override these alias by defining the symbol themselves */
+PROVIDE(_start_SupervisorSoft_trap = _start_DefaultHandler_trap);
+PROVIDE(_start_MachineSoft_trap = _start_DefaultHandler_trap);
+PROVIDE(_start_SupervisorTimer_trap = _start_DefaultHandler_trap);
+PROVIDE(_start_MachineTimer_trap = _start_DefaultHandler_trap);
+PROVIDE(_start_SupervisorExternal_trap = _start_DefaultHandler_trap);
+PROVIDE(_start_MachineExternal_trap = _start_DefaultHandler_trap);
+
 /** EXCEPTION HANDLERS **/
 
 /* Default exception handler. The riscv-rt crate provides a weak alias of this function,
@@ -44,7 +66,7 @@ PROVIDE(Breakpoint = ExceptionHandler);
 PROVIDE(LoadMisaligned = ExceptionHandler);
 PROVIDE(LoadFault = ExceptionHandler);
 PROVIDE(StoreMisaligned = ExceptionHandler);
-PROVIDE(StoreFault = ExceptionHandler);;
+PROVIDE(StoreFault = ExceptionHandler);
 PROVIDE(UserEnvCall = ExceptionHandler);
 PROVIDE(SupervisorEnvCall = ExceptionHandler);
 PROVIDE(MachineEnvCall = ExceptionHandler);

riscv-rt/macros/Cargo.toml

@@ -22,3 +22,7 @@ proc-macro2 = "1.0"
 [dependencies.syn]
 version = "1.0"
 features = ["extra-traits", "full"]
+
+[features]
+s-mode = []
+v-trap = []