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fix atomics feature #740

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Aug 3, 2023
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2 changes: 1 addition & 1 deletion .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ jobs:
- { rust: stable, vendor: Spansion, options: "--atomics" }
- { rust: stable, vendor: STMicro, options: "" }
- { rust: stable, vendor: STMicro, options: "--atomics" }
- { rust: stable, vendor: STM32-patched, options: "--strict --const_generic --pascal_enum_values --max_cluster_size --atomics" }
- { rust: stable, vendor: STM32-patched, options: "--strict --const_generic --pascal_enum_values --max_cluster_size --atomics --atomics_feature atomics" }
- { rust: stable, vendor: Toshiba, options: all }
- { rust: stable, vendor: Toshiba, options: "" }
# Test MSRV
Expand Down
1 change: 1 addition & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).

## [Unreleased]

- Fix when `atomics` features is generated but not enabled
- removed register writer & reader wrappers, generic `REG` in field writers (#731)
- Updated syn to version 2 (#732)
- Let readable field fetch doc from svd description (#734)
Expand Down
7 changes: 4 additions & 3 deletions ci/script.sh
Original file line number Diff line number Diff line change
Expand Up @@ -40,11 +40,11 @@ main() {

# test crate
cargo init --name foo $td
echo 'cortex-m = "0.7.4"' >> $td/Cargo.toml
echo 'cortex-m-rt = "0.7.1"' >> $td/Cargo.toml
echo 'cortex-m = "0.7.7"' >> $td/Cargo.toml
echo 'cortex-m-rt = "0.7.3"' >> $td/Cargo.toml
echo 'vcell = "0.1.3"' >> $td/Cargo.toml
if [[ "$options" == *"--atomics"* ]]; then
echo 'portable-atomic = { version = "0.3.16", default-features = false }' >> $td/Cargo.toml
echo 'portable-atomic = { version = "1.4", default-features = false }' >> $td/Cargo.toml
fi
echo '[profile.dev]' >> $td/Cargo.toml
echo 'incremental = false' >> $td/Cargo.toml
Expand Down Expand Up @@ -566,6 +566,7 @@ main() {
test_patched_stm32 stm32mp157
test_patched_stm32 stm32wb55
test_patched_stm32 stm32wle5
test_patched_stm32 stm32c011
;;

Toshiba)
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114 changes: 57 additions & 57 deletions src/generate/generic_atomic.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
mod atomic {
use super::*;
use portable_atomic::Ordering;

pub trait AtomicOperations {
Expand Down Expand Up @@ -35,67 +36,66 @@ mod atomic {
// Enable 64-bit atomics for 64-bit RISCV
#[cfg(any(target_pointer_width = "64", target_has_atomic = "64"))]
impl_atomics!(u64, portable_atomic::AtomicU64);
}
use atomic::AtomicOperations;

impl<REG: Readable + Writable> Reg<REG>
where
REG::Ux: AtomicOperations + Default + core::ops::Not<Output = REG::Ux>,
{
/// Set high every bit in the register that was set in the write proxy. Leave other bits
/// untouched. The write is done in a single atomic instruction.
///
/// # Safety
///
/// The resultant bit pattern may not be valid for the register.
#[inline(always)]
pub unsafe fn set_bits<F>(&self, f: F)
impl<REG: Readable + Writable> Reg<REG>
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
REG::Ux: AtomicOperations + Default + core::ops::Not<Output = REG::Ux>,
{
let bits = f(&mut W {
bits: Default::default(),
_reg: marker::PhantomData,
})
.bits;
REG::Ux::atomic_or(self.register.as_ptr(), bits);
}
/// Set high every bit in the register that was set in the write proxy. Leave other bits
/// untouched. The write is done in a single atomic instruction.
///
/// # Safety
///
/// The resultant bit pattern may not be valid for the register.
#[inline(always)]
pub unsafe fn set_bits<F>(&self, f: F)
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let bits = f(&mut W {
bits: Default::default(),
_reg: marker::PhantomData,
})
.bits;
REG::Ux::atomic_or(self.register.as_ptr(), bits);
}

/// Clear every bit in the register that was cleared in the write proxy. Leave other bits
/// untouched. The write is done in a single atomic instruction.
///
/// # Safety
///
/// The resultant bit pattern may not be valid for the register.
#[inline(always)]
pub unsafe fn clear_bits<F>(&self, f: F)
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let bits = f(&mut W {
bits: !REG::Ux::default(),
_reg: marker::PhantomData,
})
.bits;
REG::Ux::atomic_and(self.register.as_ptr(), bits);
}
/// Clear every bit in the register that was cleared in the write proxy. Leave other bits
/// untouched. The write is done in a single atomic instruction.
///
/// # Safety
///
/// The resultant bit pattern may not be valid for the register.
#[inline(always)]
pub unsafe fn clear_bits<F>(&self, f: F)
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let bits = f(&mut W {
bits: !REG::Ux::default(),
_reg: marker::PhantomData,
})
.bits;
REG::Ux::atomic_and(self.register.as_ptr(), bits);
}

/// Toggle every bit in the register that was set in the write proxy. Leave other bits
/// untouched. The write is done in a single atomic instruction.
///
/// # Safety
///
/// The resultant bit pattern may not be valid for the register.
#[inline(always)]
pub unsafe fn toggle_bits<F>(&self, f: F)
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let bits = f(&mut W {
bits: Default::default(),
_reg: marker::PhantomData,
})
.bits;
REG::Ux::atomic_xor(self.register.as_ptr(), bits);
/// Toggle every bit in the register that was set in the write proxy. Leave other bits
/// untouched. The write is done in a single atomic instruction.
///
/// # Safety
///
/// The resultant bit pattern may not be valid for the register.
#[inline(always)]
pub unsafe fn toggle_bits<F>(&self, f: F)
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let bits = f(&mut W {
bits: Default::default(),
_reg: marker::PhantomData,
})
.bits;
REG::Ux::atomic_xor(self.register.as_ptr(), bits);
}
}
}
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