small refactoring and release 0.30.2

CHANGELOG.md

@@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
 
 ## [Unreleased]
 
+## [v0.30.2] - 2023-10-22
+
+- Fix documentation warnings
 - Use `ArrayProxy` for memory disjoined register arrays
 - Use `const fn` where allowed
 
@@ -813,7 +816,8 @@ peripheral.register.write(|w| w.field().set());
 
 - Initial version of the `svd2rust` tool
 
-[Unreleased]: https://github.com/rust-embedded/svd2rust/compare/v0.30.1...HEAD
+[Unreleased]: https://github.com/rust-embedded/svd2rust/compare/v0.30.2...HEAD
+[v0.30.2]: https://github.com/rust-embedded/svd2rust/compare/v0.30.1...v0.30.2
 [v0.30.1]: https://github.com/rust-embedded/svd2rust/compare/v0.30.0...v0.30.1
 [v0.30.0]: https://github.com/rust-embedded/svd2rust/compare/v0.29.0...v0.30.0
 [v0.29.0]: https://github.com/rust-embedded/svd2rust/compare/v0.28.0...v0.29.0

Cargo.toml

@@ -23,7 +23,7 @@ keywords = [
 license = "MIT OR Apache-2.0"
 name = "svd2rust"
 repository = "https://github.com/rust-embedded/svd2rust/"
-version = "0.30.1"
+version = "0.30.2"
 readme = "README.md"
 rust-version = "1.70"
 

src/generate/generic.rs

@@ -457,18 +457,50 @@ impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
 {
     /// Field width
     pub const WIDTH: u8 = WI;
+
+    /// Writes raw bits to the field
+    ///
+    /// # Safety
+    ///
+    /// Passing incorrect value can cause undefined behaviour. See reference manual
+    #[inline(always)]
+    pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::mask::<WI>() << OF);
+        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << OF;
+        self.w
+    }
+    /// Writes `variant` to the field
+    #[inline(always)]
+    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
+        unsafe { self.bits(FI::Ux::from(variant)) }
+    }
 }
 
 impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
 {
     /// Field width
     pub const WIDTH: u8 = WI;
+
+    /// Writes raw bits to the field
+    #[inline(always)]
+    pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
+        self.w.bits &= !(REG::Ux::mask::<WI>() << OF);
+        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << OF;
+        self.w
+    }
+    /// Writes `variant` to the field
+    #[inline(always)]
+    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
+        self.bits(FI::Ux::from(variant))
+    }
 }
 
 macro_rules! bit_proxy {
@@ -486,17 +518,7 @@ macro_rules! bit_proxy {
         {
             /// Field width
             pub const WIDTH: u8 = 1;
-        }
-    };
-}
 
-macro_rules! impl_bit_proxy {
-    ($writer:ident) => {
-        impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI>
-        where
-            REG: Writable + RegisterSpec,
-            bool: From<FI>,
-        {
             /// Writes bit to the field
             #[inline(always)]
             pub fn bit(self, value: bool) -> &'a mut W<REG> {
@@ -521,57 +543,6 @@ bit_proxy!(BitWriter0S, Bit0S);
 bit_proxy!(BitWriter1T, Bit1T);
 bit_proxy!(BitWriter0T, Bit0T);
 
-impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI>
-where
-    REG: Writable + RegisterSpec,
-    FI: FieldSpec,
-    REG::Ux: From<FI::Ux>,
-{
-    /// Writes raw bits to the field
-    ///
-    /// # Safety
-    ///
-    /// Passing incorrect value can cause undefined behaviour. See reference manual
-    #[inline(always)]
-    pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::mask::<WI>() << OF);
-        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << OF;
-        self.w
-    }
-    /// Writes `variant` to the field
-    #[inline(always)]
-    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        unsafe { self.bits(FI::Ux::from(variant)) }
-    }
-}
-impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI>
-where
-    REG: Writable + RegisterSpec,
-    FI: FieldSpec,
-    REG::Ux: From<FI::Ux>,
-{
-    /// Writes raw bits to the field
-    #[inline(always)]
-    pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::mask::<WI>() << OF);
-        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << OF;
-        self.w
-    }
-    /// Writes `variant` to the field
-    #[inline(always)]
-    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        self.bits(FI::Ux::from(variant))
-    }
-}
-
-impl_bit_proxy!(BitWriter);
-impl_bit_proxy!(BitWriter1S);
-impl_bit_proxy!(BitWriter0C);
-impl_bit_proxy!(BitWriter1C);
-impl_bit_proxy!(BitWriter0S);
-impl_bit_proxy!(BitWriter1T);
-impl_bit_proxy!(BitWriter0T);
-
 impl<'a, REG, const OF: u8, FI> BitWriter<'a, REG, OF, FI>
 where
     REG: Writable + RegisterSpec,

src/generate/register.rs

@@ -95,7 +95,7 @@ pub fn render(
         );
         if name_snake_case != "cfg" {
             alias_doc += format!(
-                "\n\nFor information about available fields see [`{name_snake_case}`] module"
+                "\n\nFor information about available fields see [`mod@{name_snake_case}`] module"
             )
             .as_str();
         }

src/lib.rs

@@ -588,7 +588,7 @@ pub fn generate(input: &str, config: &Config) -> Result<Generation> {
     })
 }
 
-/// Load a [Device] from a string slice with given [config](crate::util::Config).
+/// Load a [Device](svd::Device) from a string slice with given [config](crate::util::Config).
 pub fn load_from(input: &str, config: &crate::util::Config) -> Result<svd::Device> {
     use self::util::SourceType;
     use svd_parser::ValidateLevel;

src/util.rs

@@ -183,7 +183,7 @@ pub enum SourceType {
 }
 
 impl SourceType {
-    /// Make a new [`Source`] from a given extension.
+    /// Make a new [`SourceType`] from a given extension.
     pub fn from_extension(s: &str) -> Option<Self> {
         match s {
             "svd" | "xml" => Some(Self::Xml),