write_raw

CHANGELOG.md

@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
 
 ## [Unreleased]
 
+- Add unsafe `write_bits` to all writtable registers
 - Revert #711
 - Add `defmt` impls for `TryFromInterruptError`, riscv interrupt enums
 - Fix calculating `modifiedWriteValues` bitmasks with field arrays

src/generate/generic.rs

@@ -478,7 +478,7 @@ macro_rules! bit_proxy {
             pub const fn width(&self) -> u8 {
                 Self::WIDTH
             }
-        
+
             /// Field offset
             #[inline(always)]
             pub const fn offset(&self) -> u8 {

src/generate/generic_reg_vcell.rs

@@ -179,6 +179,16 @@ impl<REG: Writable> Reg<REG> {
 
         result
     }
+
+    /// Writes raw value to register.
+    ///
+    /// # Safety
+    ///
+    /// Unsafe as it passes value without checks.
+    #[inline(always)]
+    pub unsafe fn write_bits(&self, bits: REG::Ux) {
+        self.register.set(bits);
+    }
 }
 
 impl<REG: Readable + Writable> Reg<REG> {