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Add vec_sel
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lu-zero authored and Amanieu committed Feb 23, 2024
1 parent 1940d10 commit a9887d1
Showing 1 changed file with 120 additions and 0 deletions.
120 changes: 120 additions & 0 deletions crates/core_arch/src/powerpc/altivec.rs
Original file line number Diff line number Diff line change
Expand Up @@ -478,6 +478,15 @@ macro_rules! t_t_s {
}

macro_rules! t_u {
(vector_bool_char) => {
vector_unsigned_char
};
(vector_bool_short) => {
vector_unsigned_short
};
(vector_bool_int) => {
vector_unsigned_int
};
(vector_unsigned_char) => {
vector_unsigned_char
};
Expand All @@ -496,6 +505,42 @@ macro_rules! t_u {
(vector_signed_int) => {
vector_unsigned_int
};
(vector_float) => {
vector_unsigned_int
};
}

macro_rules! t_b {
(vector_bool_char) => {
vector_bool_char
};
(vector_bool_short) => {
vector_bool_short
};
(vector_bool_int) => {
vector_bool_int
};
(vector_signed_char) => {
vector_bool_char
};
(vector_signed_short) => {
vector_bool_short
};
(vector_signed_int) => {
vector_bool_int
};
(vector_unsigned_char) => {
vector_bool_char
};
(vector_unsigned_short) => {
vector_bool_short
};
(vector_unsigned_int) => {
vector_bool_int
};
(vector_float) => {
vector_bool_int
};
}

macro_rules! impl_from {
Expand Down Expand Up @@ -2572,6 +2617,62 @@ mod sealed {

impl_vec_trait! { [VectorNand vec_nand]+ 2b (vec_vnandsb, vec_vnandsh, vec_vnandsw) }

#[inline]
#[target_feature(enable = "altivec")]
#[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vsel))]
#[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxsel))]
pub unsafe fn vec_vsel(
a: vector_signed_char,
b: vector_signed_char,
c: vector_signed_char,
) -> vector_signed_char {
let a: i8x16 = transmute(a);
let b: i8x16 = transmute(b);
let c: i8x16 = transmute(c);
let not_c = simd_xor(c, i8x16::splat(!0));

transmute(simd_or(simd_and(a, not_c), simd_and(b, c)))
}

#[unstable(feature = "stdarch_powerpc", issue = "111145")]
pub trait VectorSel<Mask> {
unsafe fn vec_sel(self, b: Self, c: Mask) -> Self;
}

macro_rules! vector_sel {
($ty: ty, $m: ty) => {
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl VectorSel<$m> for $ty {
#[inline]
#[target_feature(enable = "altivec")]
unsafe fn vec_sel(self, b: Self, c: $m) -> Self {
let a = transmute(self);
let b = transmute(b);
let c = transmute(c);

transmute(vec_vsel(a, b, c))
}
}
};
($ty: ident) => {
vector_sel! { $ty, t_b!{ $ty } }
vector_sel! { $ty, t_u!{ $ty } }
vector_sel! { t_u!{ $ty }, t_b!{ $ty } }
vector_sel! { t_u!{ $ty }, t_u!{ $ty } }
vector_sel! { t_b!{ $ty }, t_b!{ $ty } }
vector_sel! { t_b!{ $ty }, t_u!{ $ty } }
};
(- $ty: ident) => {
vector_sel! { $ty, t_b!{ $ty } }
vector_sel! { $ty, t_u!{ $ty } }
};
}

vector_sel! { vector_signed_char }
vector_sel! { vector_signed_short }
vector_sel! { vector_signed_int }
vector_sel! {- vector_float }

#[inline]
#[target_feature(enable = "altivec")]
#[cfg_attr(test, assert_instr(vcfsx, IMM5 = 1))]
Expand Down Expand Up @@ -4188,6 +4289,25 @@ pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> ve
vnmsubfp(a, b, c)
}

/// Vector Select
///
/// ## Purpose
/// Returns a vector selecting bits from two source vectors depending on the corresponding
/// bit values of a third source vector.
///
/// ## Result value
/// Each bit of r has the value of the corresponding bit of a if the corresponding
/// bit of c is 0. Otherwise, the bit of r has the value of the corresponding bit of b.
#[inline]
#[target_feature(enable = "altivec")]
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
pub unsafe fn vec_sel<T, U>(a: T, b: T, c: U) -> T
where
T: sealed::VectorSel<U>,
{
a.vec_sel(b, c)
}

/// Vector Sum Across Partial (1/4) Saturated
#[inline]
#[target_feature(enable = "altivec")]
Expand Down

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