pcie: whitelist and support mellanox connectx-2

Basic functionalities have been tested to work fine on pioneer board.
ruyisdk · Aug 18, 2024 · 66cf7c8 · 66cf7c8
1 parent fabc24f
commit 66cf7c8
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Showing 2 changed files with 2 additions and 1 deletion.
diff --git a/drivers/pci/controller/cadence/pcie-cadence-sophgo.c b/drivers/pci/controller/cadence/pcie-cadence-sophgo.c
@@ -465,6 +465,7 @@ struct vendor_id_list vendor_id_list[] = {
 	{"Inter I40E", 0x8086, 0x1572},
 	//{"WangXun RP1000", 0x8088},
 	{"Switchtec", 0x11f8,0x4052},
+	{"Mellanox ConnectX-2", 0x15b3, 0x6750}
 };
 
 size_t vendor_id_list_num = ARRAY_SIZE(vendor_id_list);

diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
@@ -47,7 +47,7 @@
 
 #define DEFAULT_UAR_PAGE_SHIFT  12
 
-#define MAX_MSIX		128
+#define MAX_MSIX		16
 #define MIN_MSIX_P_PORT		5
 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
 					 (dev_cap).num_ports * MIN_MSIX_P_PORT)