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RISC-V: fix vector insn load/store width mask #134

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RevySR merged 1 commit into ruyisdk:linux-6.6.36 from RevySR:backport-fix

Jul 11, 2024

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RevySR commented Jul 10, 2024

[ commit: 04a2aef ]

RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits. Replace GENMASK(3, 0) with GENMASK(2, 0).

Fixes: cd05483 ("riscv: Allocate user's vector context in the first-use trap")

Reviewed-by: Charlie Jenkins [email protected]
Link: https://lore.kernel.org/r/[email protected]


          RISC-V: fix vector insn load/store width mask

e0dbec6

[ commit: 04a2aef ]

RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
Replace GENMASK(3, 0) with GENMASK(2, 0).

Fixes: cd05483 ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Jesse Taube <[email protected]>
Reviewed-by: Charlie Jenkins <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Han Gao <[email protected]>
Signed-off-by: Han Gao <[email protected]>

RevySR merged commit 0c83a81 into ruyisdk:linux-6.6.36

24 of 25 checks passed

RevySR deleted the backport-fix branch

July 11, 2024 10:12

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