k230: add reboot reset,01studio dts modify

Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml

@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/canaan,k230-sysctl-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Canaan Kendryte k230 Reset Controller
+
+maintainers:
+  - Damien Le Moal <[email protected]>
+
+description: |
+  Canaan Kendryte k230 reset controller driver which supports the SoC
+  system controller supplied reset registers for the various peripherals
+  of the SoC. The k230 reset controller node must be defined as a child
+  node of the k230 system controller node.
+
+  See also:
+  - dt-bindings/reset/k230-rst.h
+
+properties:
+  compatible:
+    const: canaan,k230-sysctl-reset
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - '#reset-cells'
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/k230-rst.h>
+    sysrst: reset-controller {
+      compatible = "canaan,k230-sysctl-reset";
+      #reset-cells = <4>;
+    };

arch/riscv/boot/dts/canaan/k230-canmv-01studio.dts

@@ -28,6 +28,8 @@
 	cap-sd-highspeed;
 	rx_delay_line = <0x0d>;
 	tx_delay_line = <0xb0>;
+	clocks = <&sd0_cclk_gate>,<&sd0_cclk_gate>;
+	clock-names = "core", "bus";
 };
 &mmc_sd1{
 	status = "okay";

arch/riscv/boot/dts/canaan/k230.dtsi

@@ -213,6 +213,19 @@
 			g-tx-fifo-size = <512 1024 64 64 64 64>;
 			status = "disabled";
 		};
+		mmc_sd0: sdhci0@91580000 {
+			compatible = "kendryte,k230-dw-mshc";
+			reg = <0x0 0x91580000 0x0 0x1000>;
+			interrupts = <142 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "sdhci0irq";
+			clocks = <&dummy_sd>,<&dummy_sd>;
+			clock-names = "core", "bus";
+			max-frequency = <200000000>;
+			bus-width = <8>;
+			sdhci,auto-cmd12;
+			dma-noncoherent;
+			status = "disabled";
+		};
 
 		mmc_sd1: sdhci1@91581000 {
 			compatible = "kendryte,k230-dw-mshc";