Tiny Tapeout VHDL Demo

This is an experimental project to demonstrate how to use Tiny Tapeout to build an ASIC from VHDL. This project has not been verified - use at your own risk!

What is Tiny Tapeout?

TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

VHDL Projects

Edit the config.json and make sure that all your source files are listed under VHDL_FILES, and that DESIGN_NAME is set to the top level module name. Also update your info.yaml file with the top level module name.

The GitHub action will automatically build the ASIC files using OpenLane 2.

How to enable the GitHub actions to build the ASIC files

Please see the instructions for:

• Enabling GitHub Actions
• Enabling GitHub Pages

Resources

• FAQ
• Digital design lessons
• Learn how semiconductors work
• Join the community

What next?

• Submit your design to the next shuttle on the website. The closing date is November 4th.
• Edit this README and explain your design, how it works, and how to test it.
• Share your GDS on your social network of choice, tagging it #tinytapeout and linking Matt's profile:
  • LinkedIn #tinytapeout matt-venn
  • Mastodon #tinytapeout @matthewvenn
  • Twitter #tinytapeout @matthewvenn