vhdl.nanorc file created

vhdl.nanorc

@@ -0,0 +1,36 @@
+## Syntax highlighting for VHDL.
+
+syntax vhdl "\.vhd$"
+header "library IEEE;"
+magic "VHDL"
+comment "--"
+
+# formatter
+# linter
+
+# Types.
+color cyan "\<(bit|bit_vector|character|boolean|integer|real|time|string)\>"
+color cyan "\<(severity_level|positive|natural|signed|unsigned|line|text)\>"
+color cyan "\<(std_logic|std_logic_vector|std_ulogic|std_ulogic_vector)\>"
+color cyan "\<(qsim_state|qsim_state_vector|qsim_12state|qsim_12state_vector|qsim_strength)\>"
+color cyan "\<(mux_bit|mux_vectory|reg_bit|reg_vector|wor_bit|wor_vector)\>"
+
+# Keywords.
+color orange "\<(access|after|alias|all|architecture|array|assert|attribute|begin|block|body)\>"
+color orange "\<(buffer|bus|case|component|configuration|constant|disconnect|downto)\>"
+color orange "\<(else|elsif|end|entity|exit|file|for|function|generate|generic|group)\>"
+color orange "\<(guarded|if|impure|in|inertial|inout|is|label|library|linkage|literal)\>"
+color orange "\<(loop|map|new|next|null|of|on|open|others|out|package|port|postponed)\>"
+color orange "\<(procedure|process|pure|range|record|register|reject|report|return)\>"
+color orange "\<(select|severity|signal|shared|subtype|then|to|transport|type|unaffected)\>"
+color orange "\<(units|until|use|variable|wait|when|while|with|note|warning|error|failure)\>"
+color orange "\<(and|nand|or|nor|xor|xnor|rol|ror|sla|sll|sra|srl|mod|rem|abs|not)\>"
+
+# Booleans.
+color red "\<(true|false)\>"
+
+# Strings
+color green ""([^"\]|\\.)*""
+
+# Comments.
+color yellow "--.*"