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diff --git a/Lab1/README.md b/Lab1/README.md
@@ -1,6 +1,45 @@
 # Lab 1 亂數產生器
 
-### Before Running
+### File Structures
+
+```
+.
+├── Guideline.md
+├── README.md
+├── doc
+│   ├── Lab1_lecture.pdf
+│   ├── Lab1_quartus.pdf
+│   ├── architecture.drawio
+│   ├── machine.drawio
+│   ├── state.drawio
+│   ├── state.png
+│   └── team04_lab1_report.pdf
+├── include
+│   └── LAB1_include.sv
+├── lint
+│   └── Makefile
+├── sim
+│   ├── Top_test.py
+│   ├── Top_test.sv
+│   ├── run.sh
+│   ├── seven.py
+│   ├── tb_Top.sv
+│   └── tool.sh
+└── src
+    ├── DE2_115
+    │   ├── DE2_115.qsf
+    │   ├── DE2_115.sdc
+    │   ├── DE2_115.sv
+    │   ├── Debounce.sv
+    │   └── SevenHexDecoder.sv
+    └── Top.sv
+```
+
+### How To Run on DE2-115 with QuartusII
+
+ - [Tutorial Video](https://youtu.be/d8w0doN23KI)
+
+### Before Simulation
 
 ```shell
 cd Lab1/sim/

diff --git a/Lab2/README.md b/Lab2/README.md
@@ -1,6 +1,100 @@
 # Lab 2 RSA256 解密機
 
-### Before Running
+### File Structures
+
+```
+.
+├── Guideline.md
+├── README.md
+├── doc
+│   ├── Lab2_lecture.pdf
+│   ├── Lab2_qsys_tuto1.pdf
+│   ├── core state.drawio
+│   ├── core state.png
+│   ├── prep mont state.drawio
+│   ├── prep mont state.png
+│   ├── team04_lab2_report.pdf
+│   ├── wrapper state.drawio
+│   └── wrapper state.png
+└── src
+    ├── DE2_115
+    │   ├── DE2_115.qsf
+    │   ├── DE2_115.sdc
+    │   └── DE2_115.sv
+    ├── Rsa256Core.sv
+    ├── Rsa256Wrapper.sv
+    ├── pc_python
+    │   ├── enc.bin
+    │   ├── enc.txt
+    │   ├── golden
+    │   │   ├── core.log
+    │   │   ├── core.py
+    │   │   ├── core.sh
+    │   │   ├── dec1.txt
+    │   │   ├── dec2.txt
+    │   │   ├── dec3.txt
+    │   │   ├── enc1.bin
+    │   │   ├── enc1.txt
+    │   │   ├── enc2.bin
+    │   │   ├── enc2.txt
+    │   │   ├── enc3.bin
+    │   │   ├── enc3.txt
+    │   │   ├── key.bin
+    │   │   ├── key.txt
+    │   │   ├── key_ascii.txt
+    │   │   ├── mont.log
+    │   │   ├── mont.py
+    │   │   ├── mont.sh
+    │   │   ├── prep.log
+    │   │   ├── prep.py
+    │   │   ├── prep.sh
+    │   │   └── rsa.py
+    │   ├── key.bin
+    │   ├── key.txt
+    │   ├── rs232_python2.py
+    │   ├── rs232.cpp
+    │   └── rs232.py
+    ├── rsa_qsys
+    │   ├── rsa_qsys.bsf
+    │   ├── rsa_qsys.cmp
+    │   ├── rsa_qsys.html
+    │   ├── rsa_qsys.xml
+    │   ├── rsa_qsys_bb.v
+    │   ├── rsa_qsys_generation.rpt
+    │   ├── rsa_qsys_inst.v
+    │   ├── rsa_qsys_inst.vhd
+    │   └── synthesis
+    │       ├── rsa_qsys.debuginfo.xml
+    │       ├── rsa_qsys.qip
+    │       ├── rsa_qsys.v
+    │       └── submodules
+    │           ├── Rsa256Core.sv
+    │           ├── Rsa256Wrapper.sv
+    │           ├── altera_merlin_master_translator.sv
+    │           ├── altera_merlin_slave_translator.sv
+    │           ├── altera_reset_controller.sdc
+    │           ├── altera_reset_controller.v
+    │           ├── altera_reset_synchronizer.v
+    │           ├── rsa_qsys_altpll_0.v
+    │           ├── rsa_qsys_mm_interconnect_0.v
+    │           └── rsa_qsys_uart_0.v
+    └── tb_verilog
+        ├── PipelineCtrl.v
+        ├── PipelineTb.v
+        ├── core.sh
+        ├── tb.sv
+        ├── test_wrapper.sv
+        ├── tool.sh
+        ├── wrapper.sh
+        ├── wrapper_input.txt
+        └── wrapper_output.txt
+```
+
+### How To Run on DE2-115 with QuartusII
+
+ - [Tutorial Video](https://youtu.be/MsHFpBeLLhE)
+
+### Before Simulation
 
 ```shell
 cd Lab2/src/tb_verilog

diff --git a/Lab2/src/pc_python/rs232 old.py → Lab2/src/pc_python/rs232_python2.py b/Lab2/src/pc_python/rs232 old.py → Lab2/src/pc_python/rs232_python2.py
diff --git a/Lab2/rsa_qsys/rsa_qsys.bsf → Lab2/src/rsa_qsys/rsa_qsys.bsf b/Lab2/rsa_qsys/rsa_qsys.bsf → Lab2/src/rsa_qsys/rsa_qsys.bsf
diff --git a/Lab2/rsa_qsys/rsa_qsys.cmp → Lab2/src/rsa_qsys/rsa_qsys.cmp b/Lab2/rsa_qsys/rsa_qsys.cmp → Lab2/src/rsa_qsys/rsa_qsys.cmp
diff --git a/Lab2/rsa_qsys/rsa_qsys.html → Lab2/src/rsa_qsys/rsa_qsys.html b/Lab2/rsa_qsys/rsa_qsys.html → Lab2/src/rsa_qsys/rsa_qsys.html
diff --git a/Lab2/rsa_qsys/rsa_qsys.xml → Lab2/src/rsa_qsys/rsa_qsys.xml b/Lab2/rsa_qsys/rsa_qsys.xml → Lab2/src/rsa_qsys/rsa_qsys.xml
diff --git a/Lab2/rsa_qsys/rsa_qsys_bb.v → Lab2/src/rsa_qsys/rsa_qsys_bb.v b/Lab2/rsa_qsys/rsa_qsys_bb.v → Lab2/src/rsa_qsys/rsa_qsys_bb.v
diff --git a/Lab2/rsa_qsys/rsa_qsys_generation.rpt → Lab2/src/rsa_qsys/rsa_qsys_generation.rpt b/Lab2/rsa_qsys/rsa_qsys_generation.rpt → Lab2/src/rsa_qsys/rsa_qsys_generation.rpt
diff --git a/Lab2/rsa_qsys/rsa_qsys_inst.v → Lab2/src/rsa_qsys/rsa_qsys_inst.v b/Lab2/rsa_qsys/rsa_qsys_inst.v → Lab2/src/rsa_qsys/rsa_qsys_inst.v
diff --git a/Lab2/rsa_qsys/rsa_qsys_inst.vhd → Lab2/src/rsa_qsys/rsa_qsys_inst.vhd b/Lab2/rsa_qsys/rsa_qsys_inst.vhd → Lab2/src/rsa_qsys/rsa_qsys_inst.vhd
diff --git a/...rsa_qsys/synthesis/rsa_qsys.debuginfo.xml → ...rsa_qsys/synthesis/rsa_qsys.debuginfo.xml b/...rsa_qsys/synthesis/rsa_qsys.debuginfo.xml → ...rsa_qsys/synthesis/rsa_qsys.debuginfo.xml
diff --git a/Lab2/rsa_qsys/synthesis/rsa_qsys.qip → Lab2/src/rsa_qsys/synthesis/rsa_qsys.qip b/Lab2/rsa_qsys/synthesis/rsa_qsys.qip → Lab2/src/rsa_qsys/synthesis/rsa_qsys.qip
diff --git a/Lab2/rsa_qsys/synthesis/rsa_qsys.v → Lab2/src/rsa_qsys/synthesis/rsa_qsys.v b/Lab2/rsa_qsys/synthesis/rsa_qsys.v → Lab2/src/rsa_qsys/synthesis/rsa_qsys.v
diff --git a/...a_qsys/synthesis/submodules/Rsa256Core.sv → ...a_qsys/synthesis/submodules/Rsa256Core.sv b/...a_qsys/synthesis/submodules/Rsa256Core.sv → ...a_qsys/synthesis/submodules/Rsa256Core.sv
diff --git a/...sys/synthesis/submodules/Rsa256Wrapper.sv → ...sys/synthesis/submodules/Rsa256Wrapper.sv b/...sys/synthesis/submodules/Rsa256Wrapper.sv → ...sys/synthesis/submodules/Rsa256Wrapper.sv
diff --git a/...odules/altera_merlin_master_translator.sv → ...odules/altera_merlin_master_translator.sv b/...odules/altera_merlin_master_translator.sv → ...odules/altera_merlin_master_translator.sv
diff --git a/...modules/altera_merlin_slave_translator.sv → ...modules/altera_merlin_slave_translator.sv b/...modules/altera_merlin_slave_translator.sv → ...modules/altera_merlin_slave_translator.sv
diff --git a/...is/submodules/altera_reset_controller.sdc → ...is/submodules/altera_reset_controller.sdc b/...is/submodules/altera_reset_controller.sdc → ...is/submodules/altera_reset_controller.sdc
diff --git a/...esis/submodules/altera_reset_controller.v → ...esis/submodules/altera_reset_controller.v b/...esis/submodules/altera_reset_controller.v → ...esis/submodules/altera_reset_controller.v
diff --git a/...is/submodules/altera_reset_synchronizer.v → ...is/submodules/altera_reset_synchronizer.v b/...is/submodules/altera_reset_synchronizer.v → ...is/submodules/altera_reset_synchronizer.v
diff --git a/.../synthesis/submodules/rsa_qsys_altpll_0.v → .../synthesis/submodules/rsa_qsys_altpll_0.v b/.../synthesis/submodules/rsa_qsys_altpll_0.v → .../synthesis/submodules/rsa_qsys_altpll_0.v
diff --git a/...s/submodules/rsa_qsys_mm_interconnect_0.v → ...s/submodules/rsa_qsys_mm_interconnect_0.v b/...s/submodules/rsa_qsys_mm_interconnect_0.v → ...s/submodules/rsa_qsys_mm_interconnect_0.v
diff --git a/...ys/synthesis/submodules/rsa_qsys_uart_0.v → ...ys/synthesis/submodules/rsa_qsys_uart_0.v b/...ys/synthesis/submodules/rsa_qsys_uart_0.v → ...ys/synthesis/submodules/rsa_qsys_uart_0.v
diff --git a/Lab3/README.md b/Lab3/README.md
@@ -1,6 +1,148 @@
 # Lab 3 數位錄音機
 
-### Before Running
+### File Structures
+
+```
+.
+├── Guideline.md
+├── README.md
+├── doc
+│   ├── Lab3_lecture.pdf
+│   ├── Lab3_sup1_audiocodec.pdf
+│   ├── Lab3_sup2_mem.pdf
+│   ├── Lab3_sup3_lcd.pdf
+│   ├── Lab3_sup4_ctrlpanel.pdf
+│   ├── auddsp.drawio
+│   ├── audplayer.drawio
+│   ├── audrecorder.drawio
+│   ├── i2c.drawio
+│   ├── structure.drawio
+│   ├── team04_lab3.pdf
+│   └── top state.drawio
+├── sim
+│   ├── sh
+│   │   ├── AudDSP
+│   │   │   └── run.sh
+│   │   ├── AudPlayer
+│   │   │   └── run.sh
+│   │   ├── AudRecorder
+│   │   │   └── run.sh
+│   │   ├── I2cInitializer
+│   │   │   └── run.sh
+│   │   ├── Top
+│   │   │   └── run.sh
+│   │   └── tool.sh
+│   └── tb
+│       ├── AudDSP
+│       │   ├── data.py
+│       │   ├── golden
+│       │   │   ├── constant
+│       │   │   │   ├── constant_2.txt
+│       │   │   │   ├── constant_3.txt
+│       │   │   │   ├── constant_4.txt
+│       │   │   │   ├── constant_5.txt
+│       │   │   │   ├── constant_6.txt
+│       │   │   │   ├── constant_7.txt
+│       │   │   │   └── constant_8.txt
+│       │   │   ├── fast
+│       │   │   │   ├── fast_2.txt
+│       │   │   │   ├── fast_3.txt
+│       │   │   │   ├── fast_4.txt
+│       │   │   │   ├── fast_5.txt
+│       │   │   │   ├── fast_6.txt
+│       │   │   │   ├── fast_7.txt
+│       │   │   │   └── fast_8.txt
+│       │   │   ├── linear
+│       │   │   │   ├── linear_2.txt
+│       │   │   │   ├── linear_3.txt
+│       │   │   │   ├── linear_4.txt
+│       │   │   │   ├── linear_5.txt
+│       │   │   │   ├── linear_6.txt
+│       │   │   │   ├── linear_7.txt
+│       │   │   │   └── linear_8.txt
+│       │   │   ├── mem.txt
+│       │   │   └── normal.txt
+│       │   └── tb.sv
+│       ├── AudPlayer
+│       │   ├── golden.txt
+│       │   └── tb.sv
+│       ├── AudRecorder
+│       │   ├── data.py
+│       │   ├── golden.txt
+│       │   └── tb.sv
+│       ├── I2cInitializer
+│       │   ├── golden.txt
+│       │   ├── tb.sv
+│       │   └── tb_raw.sv
+│       └── Top
+│           ├── data.py
+│           ├── golden
+│           │   ├── constant
+│           │   │   ├── constant_2.txt
+│           │   │   ├── constant_3.txt
+│           │   │   ├── constant_4.txt
+│           │   │   ├── constant_5.txt
+│           │   │   ├── constant_6.txt
+│           │   │   ├── constant_7.txt
+│           │   │   └── constant_8.txt
+│           │   ├── fast
+│           │   │   ├── fast_2.txt
+│           │   │   ├── fast_3.txt
+│           │   │   ├── fast_4.txt
+│           │   │   ├── fast_5.txt
+│           │   │   ├── fast_6.txt
+│           │   │   ├── fast_7.txt
+│           │   │   └── fast_8.txt
+│           │   ├── linear
+│           │   │   ├── linear_2.txt
+│           │   │   ├── linear_3.txt
+│           │   │   ├── linear_4.txt
+│           │   │   ├── linear_5.txt
+│           │   │   ├── linear_6.txt
+│           │   │   ├── linear_7.txt
+│           │   │   └── linear_8.txt
+│           │   ├── mem.txt
+│           │   └── normal.txt
+│           └── tb.sv
+└── src
+    ├── Altpll
+    │   ├── Altpll.bsf
+    │   ├── Altpll.cmp
+    │   ├── Altpll.html
+    │   ├── Altpll.xml
+    │   ├── Altpll_bb.v
+    │   ├── Altpll_generation.rpt
+    │   ├── Altpll_inst.v
+    │   ├── Altpll_inst.vhd
+    │   └── synthesis
+    │       ├── Altpll.debuginfo.xml
+    │       ├── Altpll.qip
+    │       ├── Altpll.v
+    │       └── submodules
+    │           ├── Altpll_altpll_0.v
+    │           ├── altera_reset_controller.sdc
+    │           ├── altera_reset_controller.v
+    │           └── altera_reset_synchronizer.v
+    ├── AudDSP.sv
+    ├── AudPlayer.sv
+    ├── AudRecorder.sv
+    ├── DE2_115
+    │   ├── DE2_115.qsf
+    │   ├── DE2_115.sdc
+    │   ├── DE2_115.sv
+    │   ├── Debounce.sv
+    │   ├── FastSlow.sv
+    │   └── SevenHexDecoder.sv
+    ├── I2cInitializer.sv
+    └── Top.sv
+```
+
+### How To Run on DE2-115 with QuartusII
+
+ - [Tutorial Video 1](https://youtu.be/lxQ1CqLxdgA)
+ - [Tutorial Video 2](https://youtu.be/XZyHApFdQvU)
+
+### Before Simulation
 
 ```shell
 cd Lab3/sim/

diff --git a/Lab3/Altpll/Altpll.bsf → Lab3/src/Altpll/Altpll.bsf b/Lab3/Altpll/Altpll.bsf → Lab3/src/Altpll/Altpll.bsf
diff --git a/Lab3/Altpll/Altpll.cmp → Lab3/src/Altpll/Altpll.cmp b/Lab3/Altpll/Altpll.cmp → Lab3/src/Altpll/Altpll.cmp
diff --git a/Lab3/Altpll/Altpll.html → Lab3/src/Altpll/Altpll.html b/Lab3/Altpll/Altpll.html → Lab3/src/Altpll/Altpll.html
diff --git a/Lab3/Altpll/Altpll.xml → Lab3/src/Altpll/Altpll.xml b/Lab3/Altpll/Altpll.xml → Lab3/src/Altpll/Altpll.xml
diff --git a/Lab3/Altpll/Altpll_bb.v → Lab3/src/Altpll/Altpll_bb.v b/Lab3/Altpll/Altpll_bb.v → Lab3/src/Altpll/Altpll_bb.v
diff --git a/Lab3/Altpll/Altpll_generation.rpt → Lab3/src/Altpll/Altpll_generation.rpt b/Lab3/Altpll/Altpll_generation.rpt → Lab3/src/Altpll/Altpll_generation.rpt
diff --git a/Lab3/Altpll/Altpll_inst.v → Lab3/src/Altpll/Altpll_inst.v b/Lab3/Altpll/Altpll_inst.v → Lab3/src/Altpll/Altpll_inst.v
diff --git a/Lab3/Altpll/Altpll_inst.vhd → Lab3/src/Altpll/Altpll_inst.vhd b/Lab3/Altpll/Altpll_inst.vhd → Lab3/src/Altpll/Altpll_inst.vhd
diff --git a/Lab3/Altpll/synthesis/Altpll.debuginfo.xml → ...src/Altpll/synthesis/Altpll.debuginfo.xml b/Lab3/Altpll/synthesis/Altpll.debuginfo.xml → ...src/Altpll/synthesis/Altpll.debuginfo.xml
diff --git a/Lab3/Altpll/synthesis/Altpll.qip → Lab3/src/Altpll/synthesis/Altpll.qip b/Lab3/Altpll/synthesis/Altpll.qip → Lab3/src/Altpll/synthesis/Altpll.qip
diff --git a/Lab3/Altpll/synthesis/Altpll.v → Lab3/src/Altpll/synthesis/Altpll.v b/Lab3/Altpll/synthesis/Altpll.v → Lab3/src/Altpll/synthesis/Altpll.v
diff --git a/...ll/synthesis/submodules/Altpll_altpll_0.v → ...ll/synthesis/submodules/Altpll_altpll_0.v b/...ll/synthesis/submodules/Altpll_altpll_0.v → ...ll/synthesis/submodules/Altpll_altpll_0.v
diff --git a/...is/submodules/altera_reset_controller.sdc → ...is/submodules/altera_reset_controller.sdc b/...is/submodules/altera_reset_controller.sdc → ...is/submodules/altera_reset_controller.sdc
diff --git a/...esis/submodules/altera_reset_controller.v → ...esis/submodules/altera_reset_controller.v b/...esis/submodules/altera_reset_controller.v → ...esis/submodules/altera_reset_controller.v
diff --git a/...is/submodules/altera_reset_synchronizer.v → ...is/submodules/altera_reset_synchronizer.v b/...is/submodules/altera_reset_synchronizer.v → ...is/submodules/altera_reset_synchronizer.v