Merge pull request #1 from ziteh/develop

Develop

.gitignore

@@ -13,6 +13,7 @@ _autosave-*
 *-save.pro
 *-save.kicad_pcb
 fp-info-cache
+\#auto_saved_files#
 
 # Netlist files (exported from Eeschema)
 *.net
@@ -26,4 +27,6 @@ fp-info-cache
 *.csv
 
 [Gg]erber/
-*-backups/
+*-backups/
+
+*-lib-table

.vscode/settings.json

@@ -0,0 +1,3 @@
+{
+  "nrf-connect.toolchain.path": "${nrf-connect.toolchain:2.0.2}"
+}

PMW3360_PCB.pretty/16pin‐DIP(PMW3360DM-T2QU).kicad_mod

@@ -9,26 +9,26 @@
     (effects (font (size 1 1) (thickness 0.15)))
     (tstamp 5be841dc-3b4a-40c9-969b-e11a4fb210b2)
   )
-  (fp_text user "This Way Up" (at 17 -4 -90 unlocked) (layer "F.SilkS")
+  (fp_text user "This Way Up" (at 17 -4 -90 unlocked) (layer "Cmts.User")
     (effects (font (size 1 1) (thickness 0.18)))
     (tstamp af1855bf-1165-47af-a318-51c7c077dc73)
   )
   (fp_line (start -3.5 -1) (end -3.5 -10.5) (layer "F.SilkS") (width 0.2) (tstamp 0db9632a-21af-4acb-9c05-e041f8c89b3a))
   (fp_line (start 15.5 0) (end 13.5 0) (layer "F.SilkS") (width 0.2) (tstamp 158caea1-8be4-4d68-b695-e535f7813c3b))
-  (fp_line (start 16.5555 -9.238) (end 16.5555 -10.762) (layer "F.SilkS") (width 0.18) (tstamp 16834039-4a62-4b91-b724-3329ca64dfc7))
-  (fp_line (start 18.2065 -10) (end 16.5555 -9.238) (layer "F.SilkS") (width 0.18) (tstamp 2ff9d7a6-b249-453e-b010-e44f393ca31d))
-  (fp_line (start -2 0) (end -3.5 -1) (layer "F.SilkS") (width 0.2) (tstamp 35505c17-306b-4361-9895-a67ced902f2d))
+  (fp_line (start -2.3 0) (end -3.5 -1) (layer "F.SilkS") (width 0.2) (tstamp 35505c17-306b-4361-9895-a67ced902f2d))
   (fp_line (start 15.5 -10.5) (end 15.5 0) (layer "F.SilkS") (width 0.2) (tstamp 412488c3-13b7-4cf8-8c58-0304d4e5151b))
   (fp_line (start 15.5 -10.5) (end 14.5 -10.5) (layer "F.SilkS") (width 0.2) (tstamp a31240ac-8b65-44dd-ba2a-944d5c41ab25))
-  (fp_line (start 16.5555 -10.762) (end 18.2065 -10) (layer "F.SilkS") (width 0.18) (tstamp b4df3032-1614-4d87-8bc4-5dfe3ecf8672))
-  (fp_line (start -1 0) (end -2 0) (layer "F.SilkS") (width 0.2) (tstamp bdfead1f-ec4f-41f7-bfd1-971493371164))
+  (fp_line (start -1 0) (end -2.3 0) (layer "F.SilkS") (width 0.2) (tstamp bdfead1f-ec4f-41f7-bfd1-971493371164))
   (fp_line (start -3.5 -10.5) (end 0 -10.5) (layer "F.SilkS") (width 0.2) (tstamp c14d7200-f91c-4b1f-9467-64c3336c7ef2))
   (fp_circle (center 0 2.5) (end 0.3 2.5) (layer "F.SilkS") (width 0.61) (fill solid) (tstamp eb0915de-c86a-4d8e-a0f1-84dcf28d1327))
+  (fp_line (start 16.5555 -9.238) (end 16.5555 -10.762) (layer "Cmts.User") (width 0.18) (tstamp 16834039-4a62-4b91-b724-3329ca64dfc7))
+  (fp_line (start 18.2065 -10) (end 16.5555 -9.238) (layer "Cmts.User") (width 0.18) (tstamp 2ff9d7a6-b249-453e-b010-e44f393ca31d))
+  (fp_line (start 16.5555 -10.762) (end 18.2065 -10) (layer "Cmts.User") (width 0.18) (tstamp b4df3032-1614-4d87-8bc4-5dfe3ecf8672))
   (fp_rect (start -2.8 -1) (end 14.5 -9.7) (layer "Edge.Cuts") (width 0.15) (fill none) (tstamp d4edaa72-3492-434b-be68-7546139b8aef))
-  (fp_line (start 15.5 1.85) (end -3.5 1.85) (layer "F.CrtYd") (width 0.05) (tstamp 395df0a5-800c-4cca-a0f1-3ad76d2e76ca))
-  (fp_line (start -3.5 -12.55) (end 15.5 -12.55) (layer "F.CrtYd") (width 0.05) (tstamp aba0fc13-5864-4b93-a0d5-5b97e1e36281))
-  (fp_line (start -3.5 1.85) (end -3.5 -12.55) (layer "F.CrtYd") (width 0.05) (tstamp b3ee6304-4586-4924-9942-14d87bd91c7d))
-  (fp_line (start 15.5 -12.55) (end 15.5 1.85) (layer "F.CrtYd") (width 0.05) (tstamp b93d027f-21f6-4fc9-ad3f-317eded6973b))
+  (fp_line (start 15.8 1.85) (end -3.7 1.85) (layer "F.CrtYd") (width 0.05) (tstamp 395df0a5-800c-4cca-a0f1-3ad76d2e76ca))
+  (fp_line (start -3.7 -12.55) (end 15.8 -12.55) (layer "F.CrtYd") (width 0.05) (tstamp aba0fc13-5864-4b93-a0d5-5b97e1e36281))
+  (fp_line (start -3.7 1.85) (end -3.7 -12.55) (layer "F.CrtYd") (width 0.05) (tstamp b3ee6304-4586-4924-9942-14d87bd91c7d))
+  (fp_line (start 15.8 -12.55) (end 15.8 1.85) (layer "F.CrtYd") (width 0.05) (tstamp b93d027f-21f6-4fc9-ad3f-317eded6973b))
   (pad "1" thru_hole rect (at 0 0) (size 1.2 2) (drill 0.7 (offset 0 0.35)) (layers *.Cu *.Mask) (tstamp fcd8b1c2-0644-4e8e-b5df-9c237120459f))
   (pad "2" thru_hole oval (at 1.78 0) (size 1.2 2) (drill 0.7 (offset 0 0.35)) (layers *.Cu *.Mask) (tstamp b05c41f7-50e4-4be4-ab67-3c7ffa450fd9))
   (pad "3" thru_hole oval (at 3.56 0) (size 1.2 2) (drill 0.7 (offset 0 0.35)) (layers *.Cu *.Mask) (tstamp ea28b0b6-85f9-44a4-9a9d-13615241f1cc))

PMW3360_PCB/PMW3360_PCB.kicad_prl

@@ -1,7 +1,7 @@
 {
   "board": {
-    "active_layer": 37,
-    "active_layer_preset": "All Layers",
+    "active_layer": 0,
+    "active_layer_preset": "",
     "auto_track_width": true,
     "hidden_nets": [],
     "high_contrast_mode": 0,
@@ -62,7 +62,7 @@
       35,
       36
     ],
-    "visible_layers": "fffffff_ffffffff",
+    "visible_layers": "ffdffff_ffffffff",
     "zone_display_mode": 0
   },
   "meta": {

PMW3360_PCB/PMW3360_PCB.kicad_pro

@@ -34,8 +34,8 @@
         "other_text_upright": false,
         "pads": {
           "drill": 0.0,
-          "height": 1.65,
-          "width": 0.65
+          "height": 0.6,
+          "width": 1.325
         },
         "silk_line_width": 0.15,
         "silk_text_italic": false,
@@ -49,7 +49,9 @@
         }
       },
       "diff_pair_dimensions": [],
-      "drc_exclusions": [],
+      "drc_exclusions": [
+        "courtyards_overlap|235692999|150319548|1b299ce8-bb1f-4b79-95e6-5ac75a558674|2c27e078-5cb9-42fd-9d9a-a3bc492243fd"
+      ],
       "meta": {
         "version": 2
       },
@@ -79,8 +81,8 @@
         "padstack": "error",
         "pth_inside_courtyard": "ignore",
         "shorting_items": "error",
-        "silk_over_copper": "warning",
-        "silk_overlap": "warning",
+        "silk_over_copper": "ignore",
+        "silk_overlap": "ignore",
         "skew_out_of_range": "error",
         "through_hole_pad_without_hole": "error",
         "too_many_vias": "error",