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Merge pull request #732 from slaclab/synth_mode_g
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Bring out SYNTH_MODE_G generic for internal RAMs
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@ruck314
ruck314 authored Aug 31, 2020
2 parents 4b2394b + 6bd82b8 commit 25002fe
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Showing 18 changed files with 178 additions and 128 deletions.
9 changes: 6 additions & 3 deletions ethernet/EthMacCore/rtl/EthMacRx.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,9 @@ entity EthMacRx is
-- VLAN Configurations
VLAN_EN_G : boolean := false;
VLAN_SIZE_G : positive range 1 to 8 := 1;
VLAN_VID_G : Slv12Array := (0 => x"001"));
VLAN_VID_G : Slv12Array := (0 => x"001");
-- Internal RAM sythesis mode
SYNTH_MODE_G : string := "inferred");
port (
-- Clock and Reset
ethClkEn : in sl;
Expand Down Expand Up @@ -88,8 +90,9 @@ begin
-------------------
U_Import : entity surf.EthMacRxImport
generic map (
TPD_G => TPD_G,
PHY_TYPE_G => PHY_TYPE_G)
TPD_G => TPD_G,
PHY_TYPE_G => PHY_TYPE_G,
SYNTH_MODE_G => SYNTH_MODE_G)
port map (
-- Clock and reset
ethClkEn => ethClkEn,
Expand Down
8 changes: 5 additions & 3 deletions ethernet/EthMacCore/rtl/EthMacRxImport.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,9 @@ use surf.EthMacPkg.all;

entity EthMacRxImport is
generic (
TPD_G : time := 1 ns;
PHY_TYPE_G : string := "XGMII");
TPD_G : time := 1 ns;
PHY_TYPE_G : string := "XGMII";
SYNTH_MODE_G : string := "inferred");
port (
-- Clock and Reset
ethClkEn : in sl;
Expand Down Expand Up @@ -97,7 +98,8 @@ begin
U_1G : if (PHY_TYPE_G = "GMII") generate
U_GMII : entity surf.EthMacRxImportGmii
generic map (
TPD_G => TPD_G)
TPD_G => TPD_G,
SYNTH_MODE_G => SYNTH_MODE_G)
port map (
-- Clock and Reset
ethClkEn => ethClkEn,
Expand Down
10 changes: 6 additions & 4 deletions ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,8 @@ use surf.EthMacPkg.all;

entity EthMacRxImportGmii is
generic (
TPD_G : time := 1 ns);
TPD_G : time := 1 ns;
SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs
port (
-- Clock and Reset
ethClkEn : in sl;
Expand Down Expand Up @@ -111,23 +112,24 @@ begin
SLAVE_READY_EN_G => true,
VALID_THOLD_G => 1,
-- FIFO configurations
SYNTH_MODE_G => SYNTH_MODE_G,
MEMORY_TYPE_G => "distributed",
GEN_SYNC_FIFO_G => true,
CASCADE_SIZE_G => 1,
FIFO_ADDR_WIDTH_G => 4,
-- AXI Stream Port Configurations
SLAVE_AXI_CONFIG_G => AXI_CONFIG_C, -- 8-bit AXI stream interface
SLAVE_AXI_CONFIG_G => AXI_CONFIG_C, -- 8-bit AXI stream interface
MASTER_AXI_CONFIG_G => INT_EMAC_AXIS_CONFIG_C) -- 128-bit AXI stream interface
port map (
-- Slave Port
sAxisClk => ethClk,
sAxisRst => ethRst,
sAxisMaster => macMaster, -- 8-bit AXI stream interface
sAxisMaster => macMaster, -- 8-bit AXI stream interface
sAxisSlave => open,
-- Master Port
mAxisClk => ethClk,
mAxisRst => ethRst,
mAxisMaster => macIbMaster, -- 128-bit AXI stream interface
mAxisMaster => macIbMaster, -- 128-bit AXI stream interface
mAxisSlave => AXI_STREAM_SLAVE_FORCE_C);

comb : process (crcIn, crcOut, ethClkEn, ethRst, gmiiRxDv, gmiiRxEr,
Expand Down
11 changes: 8 additions & 3 deletions ethernet/EthMacCore/rtl/EthMacTop.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -147,7 +147,8 @@ begin
VLAN_EN_G => VLAN_EN_G,
VLAN_SIZE_G => VLAN_SIZE_G,
VLAN_COMMON_CLK_G => VLAN_COMMON_CLK_G,
VLAN_CONFIG_G => VLAN_CONFIG_G)
VLAN_CONFIG_G => VLAN_CONFIG_G,
SYNTH_MODE_G => SYNTH_MODE_G)
port map (
-- Master Clock and Reset
mClk => ethClk,
Expand Down Expand Up @@ -192,7 +193,9 @@ begin
-- VLAN Configurations
VLAN_EN_G => VLAN_EN_G,
VLAN_SIZE_G => VLAN_SIZE_G,
VLAN_VID_G => VLAN_VID_G)
VLAN_VID_G => VLAN_VID_G,
-- RAM sythesis Mode
SYNTH_MODE_G => SYNTH_MODE_G)
port map (
-- Clocks
ethClkEn => ethClkEn,
Expand Down Expand Up @@ -267,7 +270,9 @@ begin
-- VLAN Configurations
VLAN_EN_G => VLAN_EN_G,
VLAN_SIZE_G => VLAN_SIZE_G,
VLAN_VID_G => VLAN_VID_G)
VLAN_VID_G => VLAN_VID_G,
-- RAM Synthesis mode
SYNTH_MODE_G => SYNTH_MODE_G)
port map (
-- Clock and Reset
ethClkEn => ethClkEn,
Expand Down
9 changes: 6 additions & 3 deletions ethernet/EthMacCore/rtl/EthMacTx.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,9 @@ entity EthMacTx is
-- VLAN Configurations
VLAN_EN_G : boolean := false;
VLAN_SIZE_G : positive range 1 to 8 := 1;
VLAN_VID_G : Slv12Array := (0 => x"001"));
VLAN_VID_G : Slv12Array := (0 => x"001");
-- RAM Synthesis mode
SYNTH_MODE_G : string := "inferred");
port (
-- Clock and Reset
ethClkEn : in sl;
Expand Down Expand Up @@ -208,8 +210,9 @@ begin
-----------------------
U_Export : entity surf.EthMacTxExport
generic map (
TPD_G => TPD_G,
PHY_TYPE_G => PHY_TYPE_G)
TPD_G => TPD_G,
PHY_TYPE_G => PHY_TYPE_G,
SYNTH_MODE_G => SYNTH_MODE_G)
port map (
-- Clock and reset
ethClkEn => ethClkEn,
Expand Down
55 changes: 30 additions & 25 deletions ethernet/EthMacCore/rtl/EthMacTxCsum.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,8 @@ entity EthMacTxCsum is
DROP_ERR_PKT_G : boolean := true;
JUMBO_G : boolean := true;
VLAN_G : boolean := false;
VID_G : slv(11 downto 0) := x"001");
VID_G : slv(11 downto 0) := x"001";
SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs
port (
-- Clock and Reset
ethClk : in sl;
Expand Down Expand Up @@ -302,7 +303,7 @@ begin
v.ipv4Hdr(9) := rxMaster.tData(63 downto 56); -- Protocol
v.ipv4Hdr(12) := rxMaster.tData(87 downto 80); -- Source IP Address
v.ipv4Hdr(13) := rxMaster.tData(95 downto 88); -- Source IP Address
v.ipv4Hdr(14) := rxMaster.tData(103 downto 96); -- Source IP Address
v.ipv4Hdr(14) := rxMaster.tData(103 downto 96); -- Source IP Address
v.ipv4Hdr(15) := rxMaster.tData(111 downto 104); -- Source IP Address
v.ipv4Hdr(16) := rxMaster.tData(119 downto 112); -- Destination IP Address
v.ipv4Hdr(17) := rxMaster.tData(127 downto 120); -- Destination IP Address
Expand Down Expand Up @@ -356,32 +357,32 @@ begin
-- Check if NON-VLAN
if (VLAN_G = false) then
-- Fill in the IPv4 header checksum
v.ipv4Hdr(18) := rxMaster.tData(7 downto 0); -- Destination IP Address
v.ipv4Hdr(19) := rxMaster.tData(15 downto 8); -- Destination IP Address
v.ipv4Hdr(18) := rxMaster.tData(7 downto 0); -- Destination IP Address
v.ipv4Hdr(19) := rxMaster.tData(15 downto 8); -- Destination IP Address
-- Check for UDP data with inbound length/checksum
if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then
-- Mask off inbound UDP length/checksum
v.tData := rxMaster.tData(127 downto 80) & x"00000000" & rxMaster.tData(47 downto 0);
end if;
-- Track the number of bytes
v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C) - 2;
v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C) - 2;
v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2;
v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2;
else
-- Fill in the IPv4 header checksum
v.ipv4Hdr(14) := rxMaster.tData(7 downto 0); -- Source IP Address
v.ipv4Hdr(15) := rxMaster.tData(15 downto 8); -- Source IP Address
v.ipv4Hdr(16) := rxMaster.tData(23 downto 16); -- Destination IP Address
v.ipv4Hdr(17) := rxMaster.tData(31 downto 24); -- Destination IP Address
v.ipv4Hdr(18) := rxMaster.tData(39 downto 32); -- Destination IP Address
v.ipv4Hdr(19) := rxMaster.tData(47 downto 40); -- Destination IP Address
v.ipv4Hdr(14) := rxMaster.tData(7 downto 0); -- Source IP Address
v.ipv4Hdr(15) := rxMaster.tData(15 downto 8); -- Source IP Address
v.ipv4Hdr(16) := rxMaster.tData(23 downto 16); -- Destination IP Address
v.ipv4Hdr(17) := rxMaster.tData(31 downto 24); -- Destination IP Address
v.ipv4Hdr(18) := rxMaster.tData(39 downto 32); -- Destination IP Address
v.ipv4Hdr(19) := rxMaster.tData(47 downto 40); -- Destination IP Address
-- Check for UDP data with inbound length/checksum
if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then
-- Mask off inbound UDP length/checksum
v.tData := rxMaster.tData(127 downto 112) & x"00000000" & rxMaster.tData(79 downto 0);
end if;
-- Track the number of bytes
v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C) - 6;
v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C) - 6;
v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 6;
v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 6;
end if;
-- Check for EOF
if (rxMaster.tLast = '1') then
Expand Down Expand Up @@ -421,8 +422,8 @@ begin
end if;
end if;
-- Track the number of bytes
v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C);
v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C);
v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C);
v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C);
-- Check for EOF
if (rxMaster.tLast = '1') or (v.ipv4Len(0) > MAX_FRAME_SIZE_C) then
-- Save the EOFE value
Expand Down Expand Up @@ -460,7 +461,7 @@ begin

-- Fill in the IPv4 header
v.ipv4Hdr(2) := v.ipv4Len(0)(15 downto 8); -- IPV4_Length(15 downto 8)
v.ipv4Hdr(3) := v.ipv4Len(0)(7 downto 0); -- IPV4_Length(7 downto 0)
v.ipv4Hdr(3) := v.ipv4Len(0)(7 downto 0); -- IPV4_Length(7 downto 0)

-- Wait for the transaction data
if (tranValid = '1') and (r.tranRd = '0') then
Expand Down Expand Up @@ -642,6 +643,7 @@ begin
SLAVE_READY_EN_G => true,
VALID_THOLD_G => 1,
-- FIFO configurations
SYNTH_MODE_G => SYNTH_MODE_G,
MEMORY_TYPE_G => "block",
GEN_SYNC_FIFO_G => true,
CASCADE_SIZE_G => ite(JUMBO_G, 2, 1),
Expand All @@ -661,17 +663,19 @@ begin
mAxisMaster => mMaster,
mAxisSlave => mSlave);

Fifo_Trans : entity surf.FifoSync
Fifo_Trans : entity surf.Fifo
generic map (
TPD_G => TPD_G,
MEMORY_TYPE_G => "distributed",
FWFT_EN_G => true,
DATA_WIDTH_G => 69,
ADDR_WIDTH_G => 4,
FULL_THRES_G => 8)
TPD_G => TPD_G,
GEN_SYNC_FIFO_G => true,
SYNTH_MODE_G => SYNTH_MODE_G,
MEMORY_TYPE_G => "distributed",
FWFT_EN_G => true,
DATA_WIDTH_G => 69,
ADDR_WIDTH_G => 4,
FULL_THRES_G => 8)
port map (
clk => ethClk,
rst => ethRst,
wr_clk => ethClk,
--Write Ports (wr_clk domain)
wr_en => r.calc(0).step(EMAC_CSUM_PIPELINE_C),
din(68) => r.fragDet(EMAC_CSUM_PIPELINE_C+1),
Expand All @@ -685,6 +689,7 @@ begin
din(15 downto 0) => r.protCsum,
prog_full => tranPause,
--Read Ports (rd_clk domain)
rd_clk => ethClk,
rd_en => r.tranRd,
dout(68) => fragDet,
dout(67) => eofeDet,
Expand Down
8 changes: 5 additions & 3 deletions ethernet/EthMacCore/rtl/EthMacTxExport.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,9 @@ use surf.StdRtlPkg.all;

entity EthMacTxExport is
generic (
TPD_G : time := 1 ns;
PHY_TYPE_G : string := "XGMII");
TPD_G : time := 1 ns;
PHY_TYPE_G : string := "XGMII";
SYNTH_MODE_G : string := "inferred");
port (
-- Clock and Reset
ethClkEn : in sl;
Expand Down Expand Up @@ -87,7 +88,8 @@ begin
U_10G : if (PHY_TYPE_G = "XGMII") generate
U_XGMII : entity surf.EthMacTxExportXgmii
generic map (
TPD_G => TPD_G)
TPD_G => TPD_G,
SYNTH_MODE_G => SYNTH_MODE_G)
port map (
-- Clock and Reset
ethClk => ethClk,
Expand Down
16 changes: 9 additions & 7 deletions ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,8 @@ use surf.EthMacPkg.all;

entity EthMacTxExportXgmii is
generic (
TPD_G : time := 1 ns);
TPD_G : time := 1 ns;
SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs
port (
-- Clock and Reset
ethClk : in sl;
Expand Down Expand Up @@ -146,23 +147,24 @@ begin
SLAVE_READY_EN_G => true,
VALID_THOLD_G => 1,
-- FIFO configurations
SYNTH_MODE_G => SYNTH_MODE_G,
MEMORY_TYPE_G => "distributed",
GEN_SYNC_FIFO_G => true,
CASCADE_SIZE_G => 1,
FIFO_ADDR_WIDTH_G => 4,
-- AXI Stream Port Configurations
SLAVE_AXI_CONFIG_G => INT_EMAC_AXIS_CONFIG_C, -- 128-bit AXI stream interface
MASTER_AXI_CONFIG_G => AXI_CONFIG_C) -- 64-bit AXI stream interface
MASTER_AXI_CONFIG_G => AXI_CONFIG_C) -- 64-bit AXI stream interface
port map (
-- Slave Port
sAxisClk => ethClk,
sAxisRst => ethRst,
sAxisMaster => macObMaster, -- 128-bit AXI stream interface
sAxisMaster => macObMaster, -- 128-bit AXI stream interface
sAxisSlave => macObSlave,
-- Master Port
mAxisClk => ethClk,
mAxisRst => ethRst,
mAxisMaster => macMaster, -- 64-bit AXI stream interface
mAxisMaster => macMaster, -- 64-bit AXI stream interface
mAxisSlave => macSlave);

-- Generate read
Expand Down Expand Up @@ -340,9 +342,9 @@ begin

-- Wait for gap, min 3 clocks
if stateCount >= INTERGAP_C and stateCount >= 3 then
nxtState <= ST_IDLE_C;
nxtState <= ST_IDLE_C;
else
nxtState <= curState;
nxtState <= curState;
end if;

-- Padding frame
Expand Down Expand Up @@ -414,7 +416,7 @@ begin

-- CRC Valid
crcDataValid <= intAdvance after TPD_G;
crcIn <= intData after TPD_G;
crcIn <= intData after TPD_G;

-- Last line
if intLastLine = '1' then
Expand Down
6 changes: 5 additions & 1 deletion ethernet/EthMacCore/rtl/EthMacTxFifo.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,8 @@ entity EthMacTxFifo is
VLAN_EN_G : boolean := false;
VLAN_SIZE_G : positive := 1;
VLAN_COMMON_CLK_G : boolean := false;
VLAN_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C);
VLAN_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C;
SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs
port (
-- Master Clock and Reset
mClk : in sl;
Expand Down Expand Up @@ -79,6 +80,7 @@ begin
SLAVE_READY_EN_G => true,
VALID_THOLD_G => 1,
-- FIFO configurations
SYNTH_MODE_G => SYNTH_MODE_G,
MEMORY_TYPE_G => "distributed",
GEN_SYNC_FIFO_G => PRIM_COMMON_CLK_G,
CASCADE_SIZE_G => 1,
Expand Down Expand Up @@ -119,6 +121,7 @@ begin
SLAVE_READY_EN_G => true,
VALID_THOLD_G => 1,
-- FIFO configurations
SYNTH_MODE_G => SYNTH_MODE_G,
MEMORY_TYPE_G => "distributed",
GEN_SYNC_FIFO_G => BYP_COMMON_CLK_G,
CASCADE_SIZE_G => 1,
Expand Down Expand Up @@ -161,6 +164,7 @@ begin
SLAVE_READY_EN_G => true,
VALID_THOLD_G => 1,
-- FIFO configurations
SYNTH_MODE_G => SYNTH_MODE_G,
MEMORY_TYPE_G => "distributed",
GEN_SYNC_FIFO_G => VLAN_COMMON_CLK_G,
CASCADE_SIZE_G => 1,
Expand Down
2 changes: 2 additions & 0 deletions ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ entity GigEthGtx7 is
generic (
TPD_G : time := 1 ns;
PAUSE_EN_G : boolean := true;
SYNTH_MODE_G : string := "inferred";
-- AXI-Lite Configurations
EN_AXI_REG_G : boolean := false;
AXIL_BASE_ADDR_G : slv(31 downto 0) := X"00000000";
Expand Down Expand Up @@ -237,6 +238,7 @@ begin
PAUSE_EN_G => PAUSE_EN_G,
PAUSE_512BITS_G => PAUSE_512BITS_C,
PHY_TYPE_G => "GMII",
SYNTH_MODE_G => SYNTH_MODE_G,
PRIM_CONFIG_G => AXIS_CONFIG_G)
port map (
-- Primary Interface
Expand Down
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