Skip to content

Commit

Permalink
Merge pull request #406 from slaclab/pre-release
Browse files Browse the repository at this point in the history 
v1.9.9 release candidate
  • Loading branch information
@ruck314
ruck314 authored Apr 12, 2019
2 parents f3b19e5 + 7fd9dbc commit 29f5472
Show file tree
Hide file tree
Showing 91 changed files with 6,182 additions and 1,847 deletions.
12 changes: 6 additions & 6 deletions axi/axi-lite/rtl/AxiDualPortRam.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -85,7 +85,7 @@ architecture rtl of AxiDualPortRam is
axiReadSlave : AxiLiteReadSlaveType;
axiAddr : slv(ADDR_WIDTH_G-1 downto 0);
axiWrStrobe : slv(ADDR_AXI_WORDS_C*4-1 downto 0);
rdLatecy : natural range 0 to 3;
rdLatecy : natural range 0 to 4;
state : StateType;
end record;

Expand Down Expand Up @@ -136,7 +136,7 @@ begin
clkb => clk,
enb => en,
web => weByteMask,
rstb => rst,
rstb => '0',
addrb => addr,
dinb => din,
doutb => doutInt);
Expand Down Expand Up @@ -166,7 +166,7 @@ begin
clkb => clk,
enb => en,
web => weByteMask,
rstb => rst,
rstb => '0',
addrb => addr,
dinb => din,
doutb => doutInt);
Expand All @@ -192,7 +192,7 @@ begin
ena => en,
wea => we,
weaByte => weByte,
rsta => rst,
rsta => '0',
addra => addr,
dina => din,
douta => doutInt,
Expand Down Expand Up @@ -229,7 +229,7 @@ begin
douta => axiDout(DATA_WIDTH_G-1 downto 0),
clkb => clk,
enb => en,
rstb => rst,
rstb => '0',
addrb => addr,
doutb => doutInt);
end generate;
Expand Down Expand Up @@ -259,7 +259,7 @@ begin
enb => en, -- [in]
web => we, -- [in]
webByte => weByte, -- [in]
rstb => rst, -- [in]
rstb => '0', -- [in]
addrb => addr, -- [in]
dinb => din, -- [in]
doutb => doutInt); -- [out]
Expand Down
4 changes: 2 additions & 2 deletions axi/axi-lite/rtl/AxiVersionLegacy.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ architecture rtl of AxiVersionLegacy is
upTimeCnt : slv(31 downto 0);
timer : natural range 0 to TIMEOUT_1HZ_C;
scratchPad : slv(31 downto 0);
reloadTimer : natural range 0 to AUTO_RELOAD_TIME_G;
reloadTimer : slv(31 downto 0);
userReset : sl;
fpgaReload : sl;
haltReload : sl;
Expand All @@ -88,7 +88,7 @@ architecture rtl of AxiVersionLegacy is
upTimeCnt => (others => '0'),
timer => 0,
scratchPad => (others => '0'),
reloadTimer => 0,
reloadTimer => (others => '0'),
userReset => '1', -- Asserted on powerup
fpgaReload => '0',
haltReload => '0',
Expand Down
9 changes: 6 additions & 3 deletions axi/simlink/sim/RogueSideBand.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,9 +24,12 @@ entity RogueSideBand is port (
reset : in std_logic;
portNum : in std_logic_vector(15 downto 0);

opCode : out std_logic_vector(7 downto 0);
opCodeEn : out std_logic;
remData : out std_logic_vector(7 downto 0)
txOpCode : in std_logic_vector(7 downto 0);
txOpCodeEn : in std_logic;
txRemData : in std_logic_vector(7 downto 0);
rxOpCode : out std_logic_vector(7 downto 0);
rxOpCodeEn : out std_logic;
rxRemData : out std_logic_vector(7 downto 0)
);
end RogueSideBand;

Expand Down
28 changes: 17 additions & 11 deletions axi/simlink/sim/RogueSideBandWrap.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,15 +22,17 @@ use work.AxiStreamPkg.all;

entity RogueSideBandWrap is
generic (
TPD_G : time := 1 ns;
PORT_NUM_G : natural range 0 to 65535 := 1
);
TPD_G : time := 1 ns;
PORT_NUM_G : natural range 1024 to 49151 := 9000);
port (
sysClk : in sl;
sysRst : in sl;
opCode : out slv(7 downto 0);
opCodeEn : out sl;
remData : out slv(7 downto 0)
sysClk : in sl;
sysRst : in sl;
txOpCode : in slv(7 downto 0);
txOpCodeEn : in sl;
txRemData : in slv(7 downto 0);
rxOpCode : out slv(7 downto 0);
rxOpCodeEn : out sl;
rxRemData : out slv(7 downto 0)
);
end RogueSideBandWrap;

Expand All @@ -45,9 +47,13 @@ begin
clock => sysClk,
reset => sysRst,
portNum => toSlv(PORT_NUM_G, 16),
opCode => opCode,
opCodeEn => opCodeEn,
remData => remData);
txOpCode => txOpCode,
txOpCodeEn => txOpCodeEn,
txRemData => txRemData,
rxOpCode => rxOpCode,
rxOpCodeEn => rxOpCodeEn,
rxRemData => rxRemData);


end RogueSideBandWrap;

68 changes: 33 additions & 35 deletions axi/simlink/sim/RogueTcpMemoryWrap.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,27 +13,25 @@
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------

LIBRARY ieee;
USE work.ALL;
library ieee;
use work.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.StdRtlPkg.all;
use work.AxiLitePkg.all;

entity RogueTcpMemoryWrap is
entity RogueTcpMemoryWrap is
generic (
TPD_G : time := 1 ns;
PORT_NUM_G : natural range 0 to 65535 := 1
);
TPD_G : time := 1 ns;
PORT_NUM_G : natural range 1024 to 49151 := 9000);
port (
axilClk : in sl;
axilRst : in sl;
axilReadMaster : out AxiLiteReadMasterType;
axilReadSlave : in AxiLiteReadSlaveType;
axilWriteMaster : out AxiLiteWriteMasterType;
axilWriteSlave : in AxiLiteWriteSlaveType
);
axilClk : in sl;
axilRst : in sl;
axilReadMaster : out AxiLiteReadMasterType;
axilReadSlave : in AxiLiteReadSlaveType;
axilWriteMaster : out AxiLiteWriteMasterType;
axilWriteSlave : in AxiLiteWriteSlaveType);
end RogueTcpMemoryWrap;

-- Define architecture
Expand All @@ -44,28 +42,28 @@ begin
-- Sim Core
U_RogueTcpMemory : entity work.RogueTcpMemory
port map (
clock => axilClk,
reset => axilRst,
portNum => toSlv(PORT_NUM_G,16),
araddr => axilReadMaster.araddr,
arprot => axilReadMaster.arprot,
arvalid => axilReadMaster.arvalid,
rready => axilReadMaster.rready,
arready => axilReadSlave.arready,
rdata => axilReadSlave.rdata,
rresp => axilReadSlave.rresp,
rvalid => axilReadSlave.rvalid,
awaddr => axilWriteMaster.awaddr,
awprot => axilWriteMaster.awprot,
awvalid => axilWriteMaster.awvalid,
wdata => axilWriteMaster.wdata,
wstrb => axilWriteMaster.wstrb,
wvalid => axilWriteMaster.wvalid,
bready => axilWriteMaster.bready,
awready => axilWriteSlave.awready,
wready => axilWriteSlave.wready,
bresp => axilWriteSlave.bresp,
bvalid => axilWriteSlave.bvalid);
clock => axilClk,
reset => axilRst,
portNum => toSlv(PORT_NUM_G, 16),
araddr => axilReadMaster.araddr,
arprot => axilReadMaster.arprot,
arvalid => axilReadMaster.arvalid,
rready => axilReadMaster.rready,
arready => axilReadSlave.arready,
rdata => axilReadSlave.rdata,
rresp => axilReadSlave.rresp,
rvalid => axilReadSlave.rvalid,
awaddr => axilWriteMaster.awaddr,
awprot => axilWriteMaster.awprot,
awvalid => axilWriteMaster.awvalid,
wdata => axilWriteMaster.wdata,
wstrb => axilWriteMaster.wstrb,
wvalid => axilWriteMaster.wvalid,
bready => axilWriteMaster.bready,
awready => axilWriteSlave.awready,
wready => axilWriteSlave.wready,
bresp => axilWriteSlave.bresp,
bvalid => axilWriteSlave.bvalid);

end RogueTcpMemoryWrap;

10 changes: 5 additions & 5 deletions axi/simlink/sim/RogueTcpStreamWrap.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,11 +22,11 @@ use work.AxiStreamPkg.all;

entity RogueTcpStreamWrap is
generic (
TPD_G : time := 1 ns;
PORT_NUM_G : natural range 0 to 65535 := 1;
SSI_EN_G : boolean := true;
CHAN_COUNT_G : positive range 1 to 256 := 1;
AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C);
TPD_G : time := 1 ns;
PORT_NUM_G : natural range 1024 to 49151 := 9000;
SSI_EN_G : boolean := true;
CHAN_COUNT_G : positive range 1 to 256 := 1;
AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C);
port (
-- Clock and Reset
axisClk : in sl;
Expand Down
Loading

0 comments on commit 29f5472

Please sign in to comment.