Merge pull request #582 from slaclab/epix-dev

Updates for epix development (SACI, ssi_printf, AnalogDevices/ad9249)
slaclab · Jan 11, 2020 · 363687b · 363687b
2 parents fcc76a0 + 3d9e402
commit 363687b
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Showing 4 changed files with 18 additions and 6 deletions.
diff --git a/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd
@@ -78,6 +78,8 @@ architecture rtl of Ad9249ReadoutGroup is
       readoutDebug1  : slv16Array(NUM_CHANNELS_G-1 downto 0);
       lockedCountRst : sl;
       invert         : sl;
+      curDelayFrame  : slv(4 downto 0);
+      curDelayData   : slv5Array(NUM_CHANNELS_G-1 downto 0);
    end record;
 
    constant AXIL_REG_INIT_C : AxilRegType := (
@@ -90,7 +92,9 @@ architecture rtl of Ad9249ReadoutGroup is
       readoutDebug0  => (others => (others => '0')),
       readoutDebug1  => (others => (others => '0')),
       lockedCountRst => '0',
-      invert         => '0'
+      invert         => '0',
+      curDelayFrame  => (others => '0'),
+      curDelayData   => (others => (others => '0'))
    );
 
    signal lockedSync      : sl;
@@ -212,7 +216,9 @@ begin
 
       v.dataDelaySet        := (others => '0');
       v.frameDelaySet       := '0';
-      v.axilReadSlave.rdata := (others => '0');
+
+      v.curDelayFrame := curDelayFrame;
+      v.curDelayData  := curDelayData;
 
       -- Store last two samples read from ADC
       if (debugDataValid = '1' and axilR.freezeDebug = '0') then
@@ -235,9 +241,9 @@ begin
 
       -- Override read from r.delay and use curDealy output from delay primative instead
       for i in 0 to NUM_CHANNELS_G-1 loop
-         axiSlaveRegisterR(axilEp, X"00"+toSlv((i*4), 8), 0, curDelayData(i));
+         axiSlaveRegisterR(axilEp, X"00"+toSlv((i*4), 8), 0, axilR.curDelayData(i));
       end loop;
-      axiSlaveRegisterR(axilEp, X"20", 0, curDelayFrame);
+      axiSlaveRegisterR(axilEp, X"20", 0, axilR.curDelayFrame);
 
 
       -- Debug output to see how many times the shift has needed a relock

diff --git a/protocols/saci/rtl/SaciMaster2.vhd b/protocols/saci/rtl/SaciMaster2.vhd
@@ -69,7 +69,7 @@ architecture rtl of SaciMaster2 is
       shiftCount : slv(5 downto 0);
 
       --Saci clk gen
-      clkCount       : slv(SACI_CLK_COUNTER_SIZE_C-1 downto 0);
+      clkCount       : slv(SACI_CLK_COUNTER_SIZE_C downto 0);
       saciClkRising  : sl;
       saciClkFalling : sl;
 

diff --git a/xilinx/general/sdk/common/ssi_printf.c b/xilinx/general/sdk/common/ssi_printf.c
@@ -35,7 +35,12 @@ void ssi_putc ( void* p, char c) {
 
    // Dual port ram buffer if enabled
    if ( pp->buffSize > 0 ) {
-      Xil_Out8(pp->buffBase+4+pp->buffPtr, c);
+      //Xil_Out8(pp->buffBase+4+pp->buffPtr, c);
+      if (pp->buffPtr%4 == 0)
+         pp->buffWord = c;
+      else
+         pp->buffWord |= (c << (pp->buffPtr%4)*8);
+      Xil_Out32(pp->buffBase+4+(pp->buffPtr/4)*4, pp->buffWord);
 
       // Adjust pointer
       pp->buffPtr++;

diff --git a/xilinx/general/sdk/common/ssi_printf.h b/xilinx/general/sdk/common/ssi_printf.h
@@ -22,6 +22,7 @@ struct ssi_printf_type {
    uint16_t buffSize;
    uint16_t buffPtr;
    uint16_t buffTot;
+   uint32_t buffWord;
 };
 
 void ssi_putc ( void* p, const char c);