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Merge pull request #761 from slaclab/fir-dev
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FIR Filter Development
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@ruck314
ruck314 authored Oct 26, 2020
2 parents 3839e0d + e7bc464 commit 738c464
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Showing 12 changed files with 1,068 additions and 311 deletions.
17 changes: 3 additions & 14 deletions base/ram/inferred/DualPortRam.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ begin
end generate;

GEN_LUTRAM : if (MEMORY_TYPE_G="distributed") generate
QuadPortRam_Inst : entity surf.QuadPortRam
LutRam_Inst : entity surf.LutRam
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
Expand All @@ -107,6 +107,7 @@ begin
DATA_WIDTH_G => DATA_WIDTH_G,
BYTE_WIDTH_G => BYTE_WIDTH_G,
ADDR_WIDTH_G => ADDR_WIDTH_G,
NUM_PORTS_G => 2,
INIT_G => INIT_G)
port map (
-- Port A
Expand All @@ -123,19 +124,7 @@ begin
en_b => enb,
rstb => rstb,
addrb => addrb,
doutb => doutb,
-- Port C
clkc => '0',
en_c => '0',
rstc => FORCE_RST_C,
addrc => (others => '0'),
doutc => open,
-- Port C
clkd => '0',
en_d => '0',
rstd => FORCE_RST_C,
addrd => (others => '0'),
doutd => open);
doutb => doutb);
end generate;

end mapping;
85 changes: 43 additions & 42 deletions base/ram/inferred/OctalPortRam.vhd → base/ram/inferred/LutRam.vhd
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Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: This module infers a Quad Port RAM as distributed RAM
-- Description: This module infers distributed RAM
-- with configurable number of outputs
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
Expand All @@ -17,21 +18,21 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


library surf;
use surf.StdRtlPkg.all;

entity OctalPortRam is
entity LutRam is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low
REG_EN_G : boolean := true;
MODE_G : string := "no-change";
BYTE_WR_EN_G : boolean := false;
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
BYTE_WIDTH_G : integer := 8;
ADDR_WIDTH_G : integer range 1 to (2**24) := 4;
INIT_G : slv := "0");
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low
REG_EN_G : boolean := true;
MODE_G : string := "no-change";
BYTE_WR_EN_G : boolean := false;
DATA_WIDTH_G : positive := 16;
BYTE_WIDTH_G : positive := 8;
ADDR_WIDTH_G : positive := 4;
NUM_PORTS_G : positive;
INIT_G : slv := "0");
port (
-- Port A (Read/Write)
clka : in sl := '0';
Expand All @@ -42,51 +43,51 @@ entity OctalPortRam is
addra : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
dina : in slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
douta : out slv(DATA_WIDTH_G-1 downto 0);
-- Port B (Read Only)
-- Port B (Read Only, NUM_PORTS_G>=2)
clkb : in sl := '0';
en_b : in sl := '1';
rstb : in sl := not(RST_POLARITY_G);
addrb : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
doutb : out slv(DATA_WIDTH_G-1 downto 0);
-- Port C (Read Only)
doutb : out slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
-- Port C (Read Only, NUM_PORTS_G>=3)
en_c : in sl := '1';
clkc : in sl := '0';
rstc : in sl := not(RST_POLARITY_G);
addrc : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
doutc : out slv(DATA_WIDTH_G-1 downto 0);
-- Port D (Read Only)
doutc : out slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
-- Port D (Read Only, NUM_PORTS_G>=4)
en_d : in sl := '1';
clkd : in sl := '0';
rstd : in sl := not(RST_POLARITY_G);
addrd : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
doutd : out slv(DATA_WIDTH_G-1 downto 0);
-- Port E (Read Only)
doutd : out slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
-- Port E (Read Only, NUM_PORTS_G>=5)
en_e : in sl := '1';
clke : in sl := '0';
rste : in sl := not(RST_POLARITY_G);
addre : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
doute : out slv(DATA_WIDTH_G-1 downto 0);
-- Port F (Read Only)
doute : out slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
-- Port F (Read Only, NUM_PORTS_G>=6)
en_f : in sl := '1';
clkf : in sl := '0';
rstf : in sl := not(RST_POLARITY_G);
addrf : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
doutf : out slv(DATA_WIDTH_G-1 downto 0);
-- Port G (Read Only)
doutf : out slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
-- Port G (Read Only, NUM_PORTS_G>=7)
en_g : in sl := '1';
clkg : in sl := '0';
rstg : in sl := not(RST_POLARITY_G);
addrg : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
doutg : out slv(DATA_WIDTH_G-1 downto 0);
-- Port H (Read Only)
doutg : out slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
-- Port H (Read Only, NUM_PORTS_G>=8)
en_h : in sl := '1';
clkh : in sl := '0';
rsth : in sl := not(RST_POLARITY_G);
addrh : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');
douth : out slv(DATA_WIDTH_G-1 downto 0));
end OctalPortRam;
douth : out slv(DATA_WIDTH_G-1 downto 0) := (others => '0'));
end LutRam;

architecture rtl of OctalPortRam is
architecture rtl of LutRam is

-- Initial RAM Values
constant NUM_BYTES_C : natural := wordCount(DATA_WIDTH_G, BYTE_WIDTH_G);
Expand Down Expand Up @@ -221,7 +222,7 @@ begin
end generate;

-- Port B
PORT_B_REG : if (REG_EN_G = true) generate
PORT_B_REG : if (REG_EN_G = true) and (NUM_PORTS_G >= 2) generate
process(clkb)
begin
if rising_edge(clkb) then
Expand All @@ -234,12 +235,12 @@ begin
end process;
end generate;

PORT_B_NOT_REG : if (REG_EN_G = false) generate
PORT_B_NOT_REG : if (REG_EN_G = false) and (NUM_PORTS_G >= 2) generate
doutb <= mem(conv_integer(addrb));
end generate;

-- Port C
PORT_C_REG : if (REG_EN_G = true) generate
PORT_C_REG : if (REG_EN_G = true) and (NUM_PORTS_G >= 3) generate
process(clkc)
begin
if rising_edge(clkc) then
Expand All @@ -252,12 +253,12 @@ begin
end process;
end generate;

PORT_C_NOT_REG : if (REG_EN_G = false) generate
PORT_C_NOT_REG : if (REG_EN_G = false) and (NUM_PORTS_G >= 3) generate
doutc <= mem(conv_integer(addrc));
end generate;

-- Port D
PORT_D_REG : if (REG_EN_G = true) generate
PORT_D_REG : if (REG_EN_G = true) and (NUM_PORTS_G >= 4) generate
process(clkd)
begin
if rising_edge(clkd) then
Expand All @@ -270,12 +271,12 @@ begin
end process;
end generate;

PORT_D_NOT_REG : if (REG_EN_G = false) generate
PORT_D_NOT_REG : if (REG_EN_G = false) and (NUM_PORTS_G >= 4) generate
doutd <= mem(conv_integer(addrd));
end generate;

-- Port E
PORT_E_REG : if (REG_EN_G = true) generate
PORT_E_REG : if (REG_EN_G = true) and (NUM_PORTS_G >= 5) generate
process(clke)
begin
if rising_edge(clke) then
Expand All @@ -288,12 +289,12 @@ begin
end process;
end generate;

PORT_E_NOT_REG : if (REG_EN_G = false) generate
PORT_E_NOT_REG : if (REG_EN_G = false) and (NUM_PORTS_G >= 5) generate
doute <= mem(conv_integer(addre));
end generate;

-- Port F
PORT_F_REG : if (REG_EN_G = true) generate
PORT_F_REG : if (REG_EN_G = true) and (NUM_PORTS_G >= 6) generate
process(clkf)
begin
if rising_edge(clkf) then
Expand All @@ -306,12 +307,12 @@ begin
end process;
end generate;

PORT_F_NOT_REG : if (REG_EN_G = false) generate
PORT_F_NOT_REG : if (REG_EN_G = false) and (NUM_PORTS_G >= 6) generate
doutf <= mem(conv_integer(addrf));
end generate;

-- Port G
PORT_G_REG : if (REG_EN_G = true) generate
PORT_G_REG : if (REG_EN_G = true) and (NUM_PORTS_G >= 7) generate
process(clkg)
begin
if rising_edge(clkg) then
Expand All @@ -324,12 +325,12 @@ begin
end process;
end generate;

PORT_G_NOT_REG : if (REG_EN_G = false) generate
PORT_G_NOT_REG : if (REG_EN_G = false) and (NUM_PORTS_G >= 7) generate
doutg <= mem(conv_integer(addrg));
end generate;

-- Port H
PORT_H_REG : if (REG_EN_G = true) generate
PORT_H_REG : if (REG_EN_G = true) and (NUM_PORTS_G >= 8) generate
process(clkh)
begin
if rising_edge(clkh) then
Expand All @@ -342,7 +343,7 @@ begin
end process;
end generate;

PORT_H_NOT_REG : if (REG_EN_G = false) generate
PORT_H_NOT_REG : if (REG_EN_G = false) and (NUM_PORTS_G >= 8) generate
douth <= mem(conv_integer(addrh));
end generate;

Expand Down
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