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Merge pull request #884 from slaclab/pre-release
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Release Candidate v2.23.3
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@ruck314
ruck314 authored Jul 21, 2021
2 parents 7f14112 + 526456f commit 75c4113
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Showing 6 changed files with 943 additions and 10 deletions.
25 changes: 20 additions & 5 deletions protocols/clink/7Series/ClinkDataClk.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -95,16 +95,31 @@ begin
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => false,
STARTUP_WAIT => false,
-- CLKIN1_PERIOD => 40.0, -- 25 MHz
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT_F => 42.0, -- VCO = 1050MHz
-- CLKOUT0_DIVIDE_F => 42.0, -- 25 MHz
-- CLKOUT1_DIVIDE => 6) -- 175MHz
-----------------------------------------------------------
-- CLKIN1_PERIOD => 40.0, -- 25 MHz
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT_F => 42.0, -- VCO = 1050MHz
-- CLKOUT0_DIVIDE_F => 42.0, -- 25 MHz
-- CLKOUT1_DIVIDE => 6) -- 175MHz
-----------------------------------------------------------
-- CLKIN1_PERIOD => 25.0, -- 40 MHz
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT_F => 28.0, -- VCO = 1120MHz
-- CLKOUT0_DIVIDE_F => 28.0, -- 40 MHz
-- CLKOUT1_DIVIDE => 4) -- 280MHz
-----------------------------------------------------------
-- CLKIN1_PERIOD => 20.0, -- 50 MHz
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT_F => 21.0, -- VCO = 1050MHz
-- CLKOUT0_DIVIDE_F => 21.0, -- 50 MHz
-- CLKOUT1_DIVIDE => 3) -- 350MHz
-----------------------------------------------------------
CLKIN1_PERIOD => 11.764, -- 85 MHz (CLKIN[min.] = 43 MHz, CLKIN[max] = 102 MHz)
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 14.0, -- VCO = 1190MHz (VCO[min] = 600 MHz, VCO[max] = 1440 MHz)
CLKOUT0_DIVIDE_F => 14.0, -- 85 MHz = 1190MHz/14
CLKOUT1_DIVIDE => 2) -- 595MHz = 1190MHz/2
-----------------------------------------------------------
port map (
DCLK => sysClk,
DRDY => drpRdy,
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19 changes: 19 additions & 0 deletions python/surf/protocols/clink/_ClinkChannel.py
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Original file line number Diff line number Diff line change
Expand Up @@ -207,6 +207,21 @@ def __init__(
expand = False,
))

# Check for Imperx C1921 camera
elif (camType=='ImperxC1921'):

# Override defaults
self.BaudRate._default = 115200
self.SerThrottle._default = 10000

# Add the device
self.add(surf.protocols.clink.UartImperxC1921(
name = 'UartImperxC1921',
serial = serial,
expand = False,
))


# Check for OPA1000 camera
elif (camType=='Opal1000'):

Expand All @@ -223,6 +238,9 @@ def __init__(
# Check for Piranha4 camera
elif (camType=='Piranha4'):

# Override defaults
self.BaudRate._default = 9600

# Add the device
self.add(surf.protocols.clink.UartPiranha4(
name = 'UartPiranha4',
Expand All @@ -234,6 +252,7 @@ def __init__(
elif (camType=='Up900cl12b'):

# Override defaults
self.BaudRate._default = 9600
self.SerThrottle._default = 30000

# Add the device
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5 changes: 5 additions & 0 deletions python/surf/protocols/clink/_ClinkTop.py
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Original file line number Diff line number Diff line change
Expand Up @@ -271,10 +271,15 @@ def initialize(self):
# Same config as 85 MHz
self.Pll[i].Config85MHz()

# Check for 40 MHz configuration
if (self.PllConfig[i].get() == '40MHz'):
self.Pll[i].Config40MHz()

# Check for 25 MHz configuration
if (self.PllConfig[i].get() == '25MHz'):
self.Pll[i].Config25MHz()


# Release the reset after configuration
self.RstPll.set(0x0)

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158 changes: 158 additions & 0 deletions python/surf/protocols/clink/_ClockManager.py
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Original file line number Diff line number Diff line change
Expand Up @@ -93,6 +93,164 @@ def Config85MHz():
self.FiltReg[0].set(0x9908)
self.FiltReg[1].set(0x8100)

@self.command(description="Sets the 50 MHz configuration",)
def Config50MHz():
self.POWER.set(0xffff)
self.PHASE_MUX[0].set(0x0)
self.HIGH_TIME[0].set(0x7)
self.LOW_TIME[0].set(0x7)
self.PHASE_MUX[1].set(0x0)
self.HIGH_TIME[1].set(0x1)
self.LOW_TIME[1].set(0x1)
self.PHASE_MUX[2].set(0x0)
self.HIGH_TIME[2].set(0x1)
self.LOW_TIME[2].set(0x1)
self.PHASE_MUX[3].set(0x0)
self.HIGH_TIME[3].set(0x1)
self.LOW_TIME[3].set(0x1)
self.PHASE_MUX[4].set(0x0)
self.HIGH_TIME[4].set(0x1)
self.LOW_TIME[4].set(0x1)
self.PHASE_MUX[5].set(0x0)
self.HIGH_TIME[5].set(0x1)
self.LOW_TIME[5].set(0x1)
self.PHASE_MUX[6].set(0x0)
self.HIGH_TIME[6].set(0x1)
self.LOW_TIME[6].set(0x1)
self.PHASE_MUX_FB.set(0x0)
self.HIGH_TIME_FB.set(0x7)
self.LOW_TIME_FB.set(0x7)
self.FRAC[0].set(0x0)
self.FRAC_EN[0].set(0x0)
self.FRAC_WF_R[0].set(0x0)
self.MX[0].set(0x0)
self.EDGE[0].set(0x0)
self.NO_COUNT[0].set(0x0)
self.DELAY_TIME[0].set(0x0)
self.MX[1].set(0x0)
self.EDGE[1].set(0x0)
self.NO_COUNT[1].set(0x0)
self.DELAY_TIME[1].set(0x0)
self.MX[2].set(0x0)
self.EDGE[2].set(0x0)
self.NO_COUNT[2].set(0x1)
self.DELAY_TIME[2].set(0x0)
self.MX[3].set(0x0)
self.EDGE[3].set(0x0)
self.NO_COUNT[3].set(0x1)
self.DELAY_TIME[3].set(0x0)
self.MX[4].set(0x0)
self.EDGE[4].set(0x0)
self.NO_COUNT[4].set(0x1)
self.DELAY_TIME[4].set(0x0)
self.PHASE_MUX_F_CLKOUT[0].set(0x0)
self.FRAC_WF_F_CLKOUT[0].set(0x0)
self.MX[5].set(0x0)
self.EDGE[5].set(0x0)
self.NO_COUNT[5].set(0x1)
self.DELAY_TIME[5].set(0x0)
self.PHASE_MUX_F_CLKOUT_FB.set(0x0)
self.FRAC_WF_F_CLKOUT_FB.set(0x0)
self.MX[6].set(0x0)
self.EDGE[6].set(0x0)
self.NO_COUNT[6].set(0x1)
self.DELAY_TIME[6].set(0x0)
self.FRAC_FB.set(0x0)
self.FRAC_EN_FB.set(0x0)
self.FRAC_WF_R_FB.set(0x0)
self.MX_FB.set(0x0)
self.EDGE_FB.set(0x0)
self.NO_COUNT_FB.set(0x0)
self.DELAY_TIME_FB.set(0x0)
self.EDGE_DIV.set(0x0)
self.NO_COUNT_DIV.set(0x1)
self.HIGH_TIME_DIV.set(0x1)
self.LOW_TIME_DIV.set(0x1)
self.LockReg[0].set(0x2bc)
self.LockReg[1].set(0x7c01)
self.LockReg[2].set(0xffe9)
self.FiltReg[0].set(0x9908)
self.FiltReg[1].set(0x8100)

@self.command(description="Sets the 40 MHz configuration",)
def Config40MHz():
self.POWER.set(0xffff)
self.PHASE_MUX[0].set(0x0)
self.HIGH_TIME[0].set(0xe)
self.LOW_TIME[0].set(0xe)
self.PHASE_MUX[1].set(0x0)
self.HIGH_TIME[1].set(0x2)
self.LOW_TIME[1].set(0x2)
self.PHASE_MUX[2].set(0x0)
self.HIGH_TIME[2].set(0x1)
self.LOW_TIME[2].set(0x1)
self.PHASE_MUX[3].set(0x0)
self.HIGH_TIME[3].set(0x1)
self.LOW_TIME[3].set(0x1)
self.PHASE_MUX[4].set(0x0)
self.HIGH_TIME[4].set(0x1)
self.LOW_TIME[4].set(0x1)
self.PHASE_MUX[5].set(0x0)
self.HIGH_TIME[5].set(0x1)
self.LOW_TIME[5].set(0x1)
self.PHASE_MUX[6].set(0x0)
self.HIGH_TIME[6].set(0x1)
self.LOW_TIME[6].set(0x1)
self.PHASE_MUX_FB.set(0x0)
self.HIGH_TIME_FB.set(0xe)
self.LOW_TIME_FB.set(0xe)
self.FRAC[0].set(0x0)
self.FRAC_EN[0].set(0x0)
self.FRAC_WF_R[0].set(0x0)
self.MX[0].set(0x0)
self.EDGE[0].set(0x0)
self.NO_COUNT[0].set(0x0)
self.DELAY_TIME[0].set(0x0)
self.MX[1].set(0x0)
self.EDGE[1].set(0x0)
self.NO_COUNT[1].set(0x0)
self.DELAY_TIME[1].set(0x0)
self.MX[2].set(0x0)
self.EDGE[2].set(0x0)
self.NO_COUNT[2].set(0x1)
self.DELAY_TIME[2].set(0x0)
self.MX[3].set(0x0)
self.EDGE[3].set(0x0)
self.NO_COUNT[3].set(0x1)
self.DELAY_TIME[3].set(0x0)
self.MX[4].set(0x0)
self.EDGE[4].set(0x0)
self.NO_COUNT[4].set(0x1)
self.DELAY_TIME[4].set(0x0)
self.PHASE_MUX_F_CLKOUT[0].set(0x0)
self.FRAC_WF_F_CLKOUT[0].set(0x0)
self.MX[5].set(0x0)
self.EDGE[5].set(0x0)
self.NO_COUNT[5].set(0x1)
self.DELAY_TIME[5].set(0x0)
self.PHASE_MUX_F_CLKOUT_FB.set(0x0)
self.FRAC_WF_F_CLKOUT_FB.set(0x0)
self.MX[6].set(0x0)
self.EDGE[6].set(0x0)
self.NO_COUNT[6].set(0x1)
self.DELAY_TIME[6].set(0x0)
self.FRAC_FB.set(0x0)
self.FRAC_EN_FB.set(0x0)
self.FRAC_WF_R_FB.set(0x0)
self.MX_FB.set(0x0)
self.EDGE_FB.set(0x0)
self.NO_COUNT_FB.set(0x0)
self.DELAY_TIME_FB.set(0x0)
self.EDGE_DIV.set(0x0)
self.NO_COUNT_DIV.set(0x1)
self.HIGH_TIME_DIV.set(0x1)
self.LOW_TIME_DIV.set(0x1)
self.LockReg[0].set(0x15e)
self.LockReg[1].set(0x7c01)
self.LockReg[2].set(0xffe9)
self.FiltReg[0].set(0x908)
self.FiltReg[1].set(0x1000)

@self.command(description="Sets the 25 MHz configuration",)
def Config25MHz():
self.POWER.set(0xffff)
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