Merge pull request #211 from slaclab/pre-release

v1.8.0 release candidate
slaclab · Apr 19, 2018 · 8bee8d1 · 8bee8d1
2 parents 058604c + 50c51f7
commit 8bee8d1
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Showing 168 changed files with 4,842 additions and 1,351 deletions.
diff --git a/axi/rtl/AxiDualPortRam.vhd → axi/axi-lite/rtl/AxiDualPortRam.vhd b/axi/rtl/AxiDualPortRam.vhd → axi/axi-lite/rtl/AxiDualPortRam.vhd
diff --git a/axi/rtl/AxiLiteAsync.vhd → axi/axi-lite/rtl/AxiLiteAsync.vhd b/axi/rtl/AxiLiteAsync.vhd → axi/axi-lite/rtl/AxiLiteAsync.vhd
diff --git a/axi/rtl/AxiLiteCrossbar.vhd → axi/axi-lite/rtl/AxiLiteCrossbar.vhd b/axi/rtl/AxiLiteCrossbar.vhd → axi/axi-lite/rtl/AxiLiteCrossbar.vhd
diff --git a/axi/rtl/AxiLiteFifoPop.vhd → axi/axi-lite/rtl/AxiLiteFifoPop.vhd b/axi/rtl/AxiLiteFifoPop.vhd → axi/axi-lite/rtl/AxiLiteFifoPop.vhd
diff --git a/axi/rtl/AxiLiteFifoPush.vhd → axi/axi-lite/rtl/AxiLiteFifoPush.vhd b/axi/rtl/AxiLiteFifoPush.vhd → axi/axi-lite/rtl/AxiLiteFifoPush.vhd
diff --git a/axi/rtl/AxiLiteFifoPushPop.vhd → axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd b/axi/rtl/AxiLiteFifoPushPop.vhd → axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd
diff --git a/axi/rtl/AxiLiteMaster.vhd → axi/axi-lite/rtl/AxiLiteMaster.vhd b/axi/rtl/AxiLiteMaster.vhd → axi/axi-lite/rtl/AxiLiteMaster.vhd
diff --git a/axi/rtl/AxiLiteMasterPkg.vhd → axi/axi-lite/rtl/AxiLiteMasterPkg.vhd b/axi/rtl/AxiLiteMasterPkg.vhd → axi/axi-lite/rtl/AxiLiteMasterPkg.vhd
diff --git a/axi/rtl/AxiLitePkg.vhd → axi/axi-lite/rtl/AxiLitePkg.vhd b/axi/rtl/AxiLitePkg.vhd → axi/axi-lite/rtl/AxiLitePkg.vhd
diff --git a/axi/rtl/AxiLiteRegs.vhd → axi/axi-lite/rtl/AxiLiteRegs.vhd b/axi/rtl/AxiLiteRegs.vhd → axi/axi-lite/rtl/AxiLiteRegs.vhd
diff --git a/axi/rtl/AxiLiteRingBuffer.vhd → axi/axi-lite/rtl/AxiLiteRingBuffer.vhd b/axi/rtl/AxiLiteRingBuffer.vhd → axi/axi-lite/rtl/AxiLiteRingBuffer.vhd
diff --git a/axi/rtl/AxiLiteWriteFilter.vhd → axi/axi-lite/rtl/AxiLiteWriteFilter.vhd b/axi/rtl/AxiLiteWriteFilter.vhd → axi/axi-lite/rtl/AxiLiteWriteFilter.vhd
diff --git a/axi/rtl/AxiVersion.vhd → axi/axi-lite/rtl/AxiVersion.vhd b/axi/rtl/AxiVersion.vhd → axi/axi-lite/rtl/AxiVersion.vhd
diff --git a/axi/rtl/AxiVersionLegacy.vhd → axi/axi-lite/rtl/AxiVersionLegacy.vhd b/axi/rtl/AxiVersionLegacy.vhd → axi/axi-lite/rtl/AxiVersionLegacy.vhd
diff --git a/axi/axi-lite/ruckus.tcl b/axi/axi-lite/ruckus.tcl
@@ -0,0 +1,8 @@
+# Load RUCKUS library
+source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
+
+# Load Source Code
+loadSource -dir "$::DIR_PATH/rtl"
+
+# Load Simulation
+loadSource -sim_only -dir "$::DIR_PATH/tb"
diff --git a/axi/tb/AxiLiteAsyncTb.vhd → axi/axi-lite/tb/AxiLiteAsyncTb.vhd b/axi/tb/AxiLiteAsyncTb.vhd → axi/axi-lite/tb/AxiLiteAsyncTb.vhd
diff --git a/axi/tb/AxiLiteWriteFilterTb.vhd → axi/axi-lite/tb/AxiLiteWriteFilterTb.vhd b/axi/tb/AxiLiteWriteFilterTb.vhd → axi/axi-lite/tb/AxiLiteWriteFilterTb.vhd
diff --git a/axi/rtl/AxiStreamBytePacker.vhd → axi/axi-stream/rtl/AxiStreamBytePacker.vhd b/axi/rtl/AxiStreamBytePacker.vhd → axi/axi-stream/rtl/AxiStreamBytePacker.vhd
diff --git a/axi/rtl/AxiStreamDeMux.vhd → axi/axi-stream/rtl/AxiStreamDeMux.vhd b/axi/rtl/AxiStreamDeMux.vhd → axi/axi-stream/rtl/AxiStreamDeMux.vhd
diff --git a/axi/rtl/AxiStreamFifo.vhd → axi/axi-stream/rtl/AxiStreamFifo.vhd b/axi/rtl/AxiStreamFifo.vhd → axi/axi-stream/rtl/AxiStreamFifo.vhd
diff --git a/axi/rtl/AxiStreamFifoV2.vhd → axi/axi-stream/rtl/AxiStreamFifoV2.vhd b/axi/rtl/AxiStreamFifoV2.vhd → axi/axi-stream/rtl/AxiStreamFifoV2.vhd
diff --git a/axi/rtl/AxiStreamFlush.vhd → axi/axi-stream/rtl/AxiStreamFlush.vhd b/axi/rtl/AxiStreamFlush.vhd → axi/axi-stream/rtl/AxiStreamFlush.vhd
diff --git a/axi/rtl/AxiStreamGearboxPack.vhd → axi/axi-stream/rtl/AxiStreamGearboxPack.vhd b/axi/rtl/AxiStreamGearboxPack.vhd → axi/axi-stream/rtl/AxiStreamGearboxPack.vhd
diff --git a/axi/rtl/AxiStreamGearboxUnpack.vhd → ...axi-stream/rtl/AxiStreamGearboxUnpack.vhd b/axi/rtl/AxiStreamGearboxUnpack.vhd → ...axi-stream/rtl/AxiStreamGearboxUnpack.vhd
diff --git a/axi/rtl/AxiStreamMon.vhd → axi/axi-stream/rtl/AxiStreamMon.vhd b/axi/rtl/AxiStreamMon.vhd → axi/axi-stream/rtl/AxiStreamMon.vhd
diff --git a/axi/rtl/AxiStreamMonAxiL.vhd → axi/axi-stream/rtl/AxiStreamMonAxiL.vhd b/axi/rtl/AxiStreamMonAxiL.vhd → axi/axi-stream/rtl/AxiStreamMonAxiL.vhd
diff --git a/axi/rtl/AxiStreamMux.vhd → axi/axi-stream/rtl/AxiStreamMux.vhd b/axi/rtl/AxiStreamMux.vhd → axi/axi-stream/rtl/AxiStreamMux.vhd
diff --git a/axi/rtl/AxiStreamPipeline.vhd → axi/axi-stream/rtl/AxiStreamPipeline.vhd b/axi/rtl/AxiStreamPipeline.vhd → axi/axi-stream/rtl/AxiStreamPipeline.vhd
diff --git a/axi/rtl/AxiStreamPkg.vhd → axi/axi-stream/rtl/AxiStreamPkg.vhd b/axi/rtl/AxiStreamPkg.vhd → axi/axi-stream/rtl/AxiStreamPkg.vhd
diff --git a/axi/rtl/AxiStreamPrbsFlowCtrl.vhd → axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd b/axi/rtl/AxiStreamPrbsFlowCtrl.vhd → axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd
diff --git a/axi/rtl/AxiStreamResize.vhd → axi/axi-stream/rtl/AxiStreamResize.vhd b/axi/rtl/AxiStreamResize.vhd → axi/axi-stream/rtl/AxiStreamResize.vhd
diff --git a/axi/rtl/AxiStreamScatterGather.vhd → ...axi-stream/rtl/AxiStreamScatterGather.vhd b/axi/rtl/AxiStreamScatterGather.vhd → ...axi-stream/rtl/AxiStreamScatterGather.vhd
diff --git a/axi/rtl/AxiStreamShift.vhd → axi/axi-stream/rtl/AxiStreamShift.vhd b/axi/rtl/AxiStreamShift.vhd → axi/axi-stream/rtl/AxiStreamShift.vhd
diff --git a/axi/rtl/AxiStreamTap.vhd → axi/axi-stream/rtl/AxiStreamTap.vhd b/axi/rtl/AxiStreamTap.vhd → axi/axi-stream/rtl/AxiStreamTap.vhd
diff --git a/axi/axi-stream/ruckus.tcl b/axi/axi-stream/ruckus.tcl
@@ -0,0 +1,8 @@
+# Load RUCKUS library
+source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
+
+# Load Source Code
+loadSource -dir "$::DIR_PATH/rtl"
+
+# Load Simulation
+loadSource -sim_only -dir "$::DIR_PATH/tb"
diff --git a/axi/tb/AxiStreamBytePackerTb.vhd → axi/axi-stream/tb/AxiStreamBytePackerTb.vhd b/axi/tb/AxiStreamBytePackerTb.vhd → axi/axi-stream/tb/AxiStreamBytePackerTb.vhd
diff --git a/axi/tb/AxiStreamFlushTb.vhd → axi/axi-stream/tb/AxiStreamFlushTb.vhd b/axi/tb/AxiStreamFlushTb.vhd → axi/axi-stream/tb/AxiStreamFlushTb.vhd
diff --git a/axi/tb/AxiStreamMuxTb.vhd → axi/axi-stream/tb/AxiStreamMuxTb.vhd b/axi/tb/AxiStreamMuxTb.vhd → axi/axi-stream/tb/AxiStreamMuxTb.vhd
diff --git a/axi/tb/AxiStreamPipelineTb.vhd → axi/axi-stream/tb/AxiStreamPipelineTb.vhd b/axi/tb/AxiStreamPipelineTb.vhd → axi/axi-stream/tb/AxiStreamPipelineTb.vhd
diff --git a/axi/tb/fifo_tb.vhd → axi/axi-stream/tb/fifo_tb.vhd b/axi/tb/fifo_tb.vhd → axi/axi-stream/tb/fifo_tb.vhd
diff --git a/axi/tb/rogue_tb.vhd → axi/axi-stream/tb/rogue_tb.vhd b/axi/tb/rogue_tb.vhd → axi/axi-stream/tb/rogue_tb.vhd
diff --git a/axi/tb/stream_tb.vhd → axi/axi-stream/tb/stream_tb.vhd b/axi/tb/stream_tb.vhd → axi/axi-stream/tb/stream_tb.vhd
diff --git a/axi/tb/vcs_tb.vhd → axi/axi-stream/tb/vcs_tb.vhd b/axi/tb/vcs_tb.vhd → axi/axi-stream/tb/vcs_tb.vhd
diff --git a/axi/rtl/AxiMemTester.vhd → axi/axi4/rtl/AxiMemTester.vhd b/axi/rtl/AxiMemTester.vhd → axi/axi4/rtl/AxiMemTester.vhd
diff --git a/axi/rtl/AxiPkg.vhd → axi/axi4/rtl/AxiPkg.vhd b/axi/rtl/AxiPkg.vhd → axi/axi4/rtl/AxiPkg.vhd
diff --git a/axi/rtl/AxiReadEmulate.vhd → axi/axi4/rtl/AxiReadEmulate.vhd b/axi/rtl/AxiReadEmulate.vhd → axi/axi4/rtl/AxiReadEmulate.vhd
diff --git a/axi/rtl/AxiReadPathFifo.vhd → axi/axi4/rtl/AxiReadPathFifo.vhd b/axi/rtl/AxiReadPathFifo.vhd → axi/axi4/rtl/AxiReadPathFifo.vhd
diff --git a/axi/rtl/AxiReadPathMux.vhd → axi/axi4/rtl/AxiReadPathMux.vhd b/axi/rtl/AxiReadPathMux.vhd → axi/axi4/rtl/AxiReadPathMux.vhd
diff --git a/axi/rtl/AxiWriteEmulate.vhd → axi/axi4/rtl/AxiWriteEmulate.vhd b/axi/rtl/AxiWriteEmulate.vhd → axi/axi4/rtl/AxiWriteEmulate.vhd
diff --git a/axi/rtl/AxiWritePathFifo.vhd → axi/axi4/rtl/AxiWritePathFifo.vhd b/axi/rtl/AxiWritePathFifo.vhd → axi/axi4/rtl/AxiWritePathFifo.vhd
diff --git a/axi/rtl/AxiWritePathMux.vhd → axi/axi4/rtl/AxiWritePathMux.vhd b/axi/rtl/AxiWritePathMux.vhd → axi/axi4/rtl/AxiWritePathMux.vhd
diff --git a/axi/axi4/ruckus.tcl b/axi/axi4/ruckus.tcl
@@ -0,0 +1,8 @@
+# Load RUCKUS library
+source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
+
+# Load Source Code
+loadSource -dir "$::DIR_PATH/rtl"
+
+# Load Simulation
+loadSource -sim_only -dir "$::DIR_PATH/tb"
diff --git a/axi/tb/AxiPkgTb.vhd → axi/axi4/tb/AxiPkgTb.vhd b/axi/tb/AxiPkgTb.vhd → axi/axi4/tb/AxiPkgTb.vhd
diff --git a/axi/rtl/AxiLiteToDrp.vhd → axi/bridge/rtl/AxiLiteToDrp.vhd b/axi/rtl/AxiLiteToDrp.vhd → axi/bridge/rtl/AxiLiteToDrp.vhd
diff --git a/axi/rtl/AxiToAxiLite.vhd → axi/bridge/rtl/AxiToAxiLite.vhd b/axi/rtl/AxiToAxiLite.vhd → axi/bridge/rtl/AxiToAxiLite.vhd
diff --git a/axi/rtl/SlvArraytoAxiLite.vhd → axi/bridge/rtl/SlvArraytoAxiLite.vhd b/axi/rtl/SlvArraytoAxiLite.vhd → axi/bridge/rtl/SlvArraytoAxiLite.vhd
diff --git a/axi/bridge/ruckus.tcl b/axi/bridge/ruckus.tcl
@@ -0,0 +1,8 @@
+# Load RUCKUS library
+source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
+
+# Load Source Code
+loadSource -dir "$::DIR_PATH/rtl"
+
+# # Load Simulation
+# loadSource -sim_only -dir "$::DIR_PATH/tb"
diff --git a/axi/rtl/AxiDmaPkg.vhd → axi/dma/rtl/AxiDmaPkg.vhd b/axi/rtl/AxiDmaPkg.vhd → axi/dma/rtl/AxiDmaPkg.vhd
diff --git a/axi/rtl/AxiStreamDma.vhd → axi/dma/rtl/AxiStreamDma.vhd b/axi/rtl/AxiStreamDma.vhd → axi/dma/rtl/AxiStreamDma.vhd
diff --git a/axi/rtl/AxiStreamDmaRead.vhd → axi/dma/rtl/AxiStreamDmaRead.vhd b/axi/rtl/AxiStreamDmaRead.vhd → axi/dma/rtl/AxiStreamDmaRead.vhd
diff --git a/axi/rtl/AxiStreamDmaRingPkg.vhd → axi/dma/rtl/AxiStreamDmaRingPkg.vhd b/axi/rtl/AxiStreamDmaRingPkg.vhd → axi/dma/rtl/AxiStreamDmaRingPkg.vhd
diff --git a/axi/rtl/AxiStreamDmaRingRead.vhd → axi/dma/rtl/AxiStreamDmaRingRead.vhd b/axi/rtl/AxiStreamDmaRingRead.vhd → axi/dma/rtl/AxiStreamDmaRingRead.vhd
diff --git a/axi/rtl/AxiStreamDmaRingWrite.vhd → axi/dma/rtl/AxiStreamDmaRingWrite.vhd b/axi/rtl/AxiStreamDmaRingWrite.vhd → axi/dma/rtl/AxiStreamDmaRingWrite.vhd
diff --git a/axi/rtl/AxiStreamDmaV2.vhd → axi/dma/rtl/AxiStreamDmaV2.vhd b/axi/rtl/AxiStreamDmaV2.vhd → axi/dma/rtl/AxiStreamDmaV2.vhd
diff --git a/axi/rtl/AxiStreamDmaV2Desc.vhd → axi/dma/rtl/AxiStreamDmaV2Desc.vhd b/axi/rtl/AxiStreamDmaV2Desc.vhd → axi/dma/rtl/AxiStreamDmaV2Desc.vhd
diff --git a/axi/rtl/AxiStreamDmaV2DescEmulate.vhd → axi/dma/rtl/AxiStreamDmaV2DescEmulate.vhd b/axi/rtl/AxiStreamDmaV2DescEmulate.vhd → axi/dma/rtl/AxiStreamDmaV2DescEmulate.vhd
diff --git a/axi/rtl/AxiStreamDmaV2Read.vhd → axi/dma/rtl/AxiStreamDmaV2Read.vhd b/axi/rtl/AxiStreamDmaV2Read.vhd → axi/dma/rtl/AxiStreamDmaV2Read.vhd
diff --git a/axi/rtl/AxiStreamDmaV2Write.vhd → axi/dma/rtl/AxiStreamDmaV2Write.vhd b/axi/rtl/AxiStreamDmaV2Write.vhd → axi/dma/rtl/AxiStreamDmaV2Write.vhd
diff --git a/axi/rtl/AxiStreamDmaWrite.vhd → axi/dma/rtl/AxiStreamDmaWrite.vhd b/axi/rtl/AxiStreamDmaWrite.vhd → axi/dma/rtl/AxiStreamDmaWrite.vhd
diff --git a/axi/dma/ruckus.tcl b/axi/dma/ruckus.tcl
@@ -0,0 +1,8 @@
+# Load RUCKUS library
+source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
+
+# Load Source Code
+loadSource -dir "$::DIR_PATH/rtl"
+
+# Load Simulation
+loadSource -sim_only -dir "$::DIR_PATH/tb"
diff --git a/axi/tb/dma_read_tb.vhd → axi/dma/tb/dma_read_tb.vhd b/axi/tb/dma_read_tb.vhd → axi/dma/tb/dma_read_tb.vhd
diff --git a/axi/tb/dma_tb.vhd → axi/dma/tb/dma_tb.vhd b/axi/tb/dma_tb.vhd → axi/dma/tb/dma_tb.vhd
diff --git a/axi/ruckus.tcl b/axi/ruckus.tcl
@@ -2,8 +2,11 @@
 source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
 
 # Load Source Code
-loadSource -dir "$::DIR_PATH/rtl/"
+loadRuckusTcl "$::DIR_PATH/axi4"
+loadRuckusTcl "$::DIR_PATH/axi-lite"
+loadRuckusTcl "$::DIR_PATH/axi-stream"
+loadRuckusTcl "$::DIR_PATH/bridge"
+loadRuckusTcl "$::DIR_PATH/dma"
 
 # Load Simulation
-loadSource -sim_only -dir "$::DIR_PATH/tb/"
 loadSource -sim_only -dir "$::DIR_PATH/simlink/sim"
diff --git a/devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd b/devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd
@@ -0,0 +1,89 @@
+-------------------------------------------------------------------------------
+-- File       : AxiMicronMt28ewCore.vhd
+-- Company    : SLAC National Accelerator Laboratory
+-- Created    : 2018-04-10
+-- Last update: 2018-04-11
+-------------------------------------------------------------------------------
+-- Description: AXI-Lite interface to Micron MT28EW FLASH IC
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the 
+-- top-level directory of this distribution and at: 
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 
+-- No part of 'SLAC Firmware Standard Library', including this file, 
+-- may be copied, modified, propagated, or distributed except according to 
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.StdRtlPkg.all;
+use work.AxiLitePkg.all;
+use work.AxiMicronMt28ewPkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity AxiMicronMt28ewCore is
+   generic (
+      TPD_G           : time             := 1 ns;
+      MEM_ADDR_MASK_G : slv(31 downto 0) := x"00000000";
+      AXI_CLK_FREQ_G  : real             := 200.0E+6);  -- units of Hz
+   port (
+      -- FLASH Interface 
+      flashInOut     : inout AxiMicronMt28ewInOutType;
+      flashOut       : out   AxiMicronMt28ewOutType;
+      -- AXI-Lite Register Interface
+      axiReadMaster  : in    AxiLiteReadMasterType;
+      axiReadSlave   : out   AxiLiteReadSlaveType;
+      axiWriteMaster : in    AxiLiteWriteMasterType;
+      axiWriteSlave  : out   AxiLiteWriteSlaveType;
+      -- Clocks and Resets
+      axiClk         : in    sl;
+      axiRst         : in    sl);
+end AxiMicronMt28ewCore;
+
+architecture mapping of AxiMicronMt28ewCore is
+
+   signal flashDin  : slv(15 downto 0);
+   signal flashDout : slv(15 downto 0);
+   signal flashTri  : sl;
+
+begin
+
+   GEN_IOBUF :
+   for i in 15 downto 0 generate
+      IOBUF_inst : IOBUF
+         port map (
+            O  => flashDout(i),         -- Buffer output
+            IO => flashInOut.dq(i),  -- Buffer inout port (connect directly to top-level port)
+            I  => flashDin(i),          -- Buffer input
+            T  => flashTri);  -- 3-state enable input, high=input, low=output     
+   end generate GEN_IOBUF;
+
+   U_CTRL : entity work.AxiMicronMt28ewReg
+      generic map (
+         TPD_G           => TPD_G,
+         MEM_ADDR_MASK_G => MEM_ADDR_MASK_G,
+         AXI_CLK_FREQ_G  => AXI_CLK_FREQ_G)
+      port map (
+         -- FLASH Interface 
+         flashAddr      => flashOut.addr,
+         flashRstL      => flashOut.rstL,
+         flashCeL       => flashOut.ceL,
+         flashOeL       => flashOut.oeL,
+         flashWeL       => flashOut.weL,
+         flashDin       => flashDin,
+         flashDout      => flashDout,
+         flashTri       => flashTri,
+         -- AXI-Lite Register Interface
+         axiReadMaster  => axiReadMaster,
+         axiReadSlave   => axiReadSlave,
+         axiWriteMaster => axiWriteMaster,
+         axiWriteSlave  => axiWriteSlave,
+         -- Clocks and Resets
+         axiClk         => axiClk,
+         axiRst         => axiRst);
+
+end mapping;
diff --git a/devices/Micron/mt28ew/rtl/AxiMicronMt28ewPkg.vhd b/devices/Micron/mt28ew/rtl/AxiMicronMt28ewPkg.vhd
@@ -0,0 +1,41 @@
+-------------------------------------------------------------------------------
+-- File       : AxiMicronMt28ewPkg.vhd
+-- Company    : SLAC National Accelerator Laboratory
+-- Created    : 2018-04-10
+-- Last update: 2018-04-10
+-------------------------------------------------------------------------------
+-- Description: AxiMicronMt28ew Package File
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the 
+-- top-level directory of this distribution and at: 
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 
+-- No part of 'SLAC Firmware Standard Library', including this file, 
+-- may be copied, modified, propagated, or distributed except according to 
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.StdRtlPkg.all;
+
+package AxiMicronMt28ewPkg is
+
+   type AxiMicronMt28ewInOutType is record
+      dq : slv(15 downto 0);
+   end record;
+   type AxiMicronMt28ewInOutArray is array (natural range <>) of AxiMicronMt28ewInOutType;
+   type AxiMicronMt28ewInOutVectorArray is array (integer range<>, integer range<>)of AxiMicronMt28ewInOutType;
+
+   type AxiMicronMt28ewOutType is record
+      ceL  : sl;
+      oeL  : sl;
+      weL  : sl;
+      addr : slv(25 downto 0);
+      rstL : sl;
+   end record;
+   type AxiMicronMt28ewOutArray is array (natural range <>) of AxiMicronMt28ewOutType;
+   type AxiMicronMt28ewOutVectorArray is array (integer range<>, integer range<>)of AxiMicronMt28ewOutType;
+
+end package;