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Merge pull request #1160 from slaclab/pre-release
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Release Candidate v2.48.0
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ruck314 authored Jun 18, 2024
2 parents 5f0ba38 + e879b47 commit a90807c
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Showing 17 changed files with 436 additions and 29 deletions.
81 changes: 60 additions & 21 deletions axi/axi-stream/rtl/AxiStreamRingBuffer.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -152,11 +152,26 @@ architecture rtl of AxiStreamRingBuffer is
signal firstAddr : slv(RAM_ADDR_WIDTH_G-1 downto 0);
signal bufferLength : slv(RAM_ADDR_WIDTH_G-1 downto 0);

signal readReq : sl;
signal armed : sl;
signal readReq : sl;
signal armed : sl;
signal fifoRst : sl;
signal axilRstSync : sl;
signal dataRstSync : sl;

signal txSlave : AxiStreamSlaveType;

-- attribute dont_touch : string;
-- attribute dont_touch of dataR : signal is "TRUE";
-- attribute dont_touch of softTrigSync : signal is "TRUE";
-- attribute dont_touch of bufferClearSync : signal is "TRUE";
-- attribute dont_touch of axilR : signal is "TRUE";
-- attribute dont_touch of readReq : signal is "TRUE";
-- attribute dont_touch of armed : signal is "TRUE";
-- attribute dont_touch of fifoRst : signal is "TRUE";
-- attribute dont_touch of axilRstSync : signal is "TRUE";
-- attribute dont_touch of dataRstSync : signal is "TRUE";
-- attribute dont_touch of txSlave : signal is "TRUE";

begin

----------------------
Expand All @@ -179,7 +194,6 @@ begin
dina => dataR.ramWrData,
-- Port B
clkb => axilClk,
rstb => axilRst,
addrb => axilR.ramRdAddr,
doutb => ramRdData);
end generate;
Expand All @@ -201,7 +215,6 @@ begin
dina => dataR.ramWrData,
-- Port B
clkb => axilClk,
rstb => axilRst,
addrb => axilR.ramRdAddr,
doutb => ramRdData);
end generate;
Expand All @@ -223,7 +236,6 @@ begin
dina => dataR.ramWrData,
-- Port B
clkb => axilClk,
rstb => axilRst,
addrb => axilR.ramRdAddr,
doutb => ramRdData);
end generate;
Expand All @@ -233,22 +245,28 @@ begin
--------------------------------------------------
U_SyncVec_dataClk : entity surf.SynchronizerVector
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
WIDTH_G => 2)
TPD_G => TPD_G,
WIDTH_G => 2)
port map (
clk => dataClk,
rst => dataRst,
dataIn(0) => axilR.softTrig,
dataIn(1) => axilR.bufferClear,
dataOut(0) => softTrigSync,
dataOut(1) => bufferClearSync);

U_RstSync_axilRst : entity surf.RstSync
generic map (
TPD_G => TPD_G)
port map (
clk => dataClk,
asyncRst => axilRst,
syncRst => axilRstSync);

--------------------------
-- Main AXI-Stream process
--------------------------
dataComb : process (bufferClearSync, dataR, dataRst, dataValid, dataValue,
extTrig, softTrigSync) is
dataComb : process (axilRstSync, bufferClearSync, dataR, dataRst, dataValid,
dataValue, extTrig, softTrigSync) is
variable v : DataRegType;
begin
-- Latch the current value
Expand Down Expand Up @@ -297,7 +315,7 @@ begin
end if;

-- Synchronous Reset
if (RST_ASYNC_G = false and dataRst = '1') or (bufferClearSync = '1') then
if (RST_ASYNC_G = false and dataRst = '1') or (bufferClearSync = '1') or (axilRstSync = '1') then
v := DATA_REG_INIT_C;
end if;

Expand All @@ -324,7 +342,7 @@ begin
RST_ASYNC_G => RST_ASYNC_G,
DATA_WIDTH_G => 2*RAM_ADDR_WIDTH_G)
port map (
rst => axilRst,
rst => fifoRst,
-- Write Interface
wr_clk => dataClk,
wr_en => dataR.readReq,
Expand All @@ -334,6 +352,8 @@ begin
valid => readReq,
dout => fifoDout);

fifoRst <= dataRst or axilRst;

fifoDin(1*RAM_ADDR_WIDTH_G-1 downto 0*RAM_ADDR_WIDTH_G) <= dataR.firstAddr;
fifoDin(2*RAM_ADDR_WIDTH_G-1 downto 1*RAM_ADDR_WIDTH_G) <= dataR.bufferLength;

Expand All @@ -342,29 +362,33 @@ begin

U_SyncVec_axilClk : entity surf.SynchronizerVector
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
WIDTH_G => 1)
TPD_G => TPD_G,
WIDTH_G => 1)
port map (
clk => axilClk,
rst => axilRst,
dataIn(0) => dataR.armed,
dataOut(0) => armed);

U_RstSync_dataRst : entity surf.RstSync
generic map (
TPD_G => TPD_G)
port map (
clk => axilClk,
asyncRst => dataRst,
syncRst => dataRstSync);

------------------------
-- Main AXI-Lite process
------------------------
axiComb : process (armed, axilR, axilReadMaster, axilRst, axilWriteMaster,
bufferLength, firstAddr, ramRdData, readReq, txSlave) is
bufferLength, dataRstSync, firstAddr, ramRdData, readReq,
txSlave) is
variable v : AxilRegType;
variable axilEp : AxiLiteEndpointType;
begin
-- Latch the current value
v := axilR;

-- Reset strobe
v.bufferClear := '0';

------------------------
-- AXI-Lite Transactions
------------------------
Expand Down Expand Up @@ -486,13 +510,28 @@ begin

-- Check if armed de-asserted
if (armed = '0') then

-- Reset the flag
v.bufferClear := '0';

-- Next states
v.dataState := IDLE_S;
v.trigState := IDLE_S;

end if;
----------------------------------------------------------------------
end case;

-- Check for external data reset
if (dataRstSync = '1') then
-- Reset the flags
v.bufferClear := '0';
v.softTrig := '0';
-- Next states
v.dataState := IDLE_S;
v.trigState := IDLE_S;
end if;

-- Update RAM read address
v.ramRdAddr := firstAddr + v.wordCnt;

Expand Down
100 changes: 100 additions & 0 deletions python/surf/devices/linear/_Ltc3815.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,100 @@
#-----------------------------------------------------------------------------
# This file is part of the 'SLAC Firmware Standard Library'. It is subject to
# the license terms in the LICENSE.txt file found in the top-level directory
# of this distribution and at:
# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
# No part of the 'SLAC Firmware Standard Library', including this file, may be
# copied, modified, propagated, or distributed except according to the terms
# contained in the LICENSE.txt file.
#-----------------------------------------------------------------------------

import pyrogue as pr

import surf.protocols.i2c

class Ltc3815(surf.protocols.i2c.PMBus):
def __init__(self, **kwargs):
super().__init__(**kwargs)

self.add(pr.LinkVariable(
name = 'Vin',
mode = 'RO',
units = 'V',
typeStr = "Float32",
disp = '{:1.3f}',
linkedGet = lambda read: self.READ_VIN.get(read=read)*4.0E-3, # Conversion factor: 4mV/Bit
dependencies = [self.READ_VIN],
))

self.add(pr.LinkVariable(
name = 'Iin',
mode = 'RO',
units = 'A',
typeStr = "Float32",
disp = '{:1.3f}',
linkedGet = lambda read: self.READ_IIN.get(read=read)*10.0E-3, # Conversion factor: 10mA/Bit
dependencies = [self.READ_IIN],
))

self.add(pr.LinkVariable(
name = 'Vout',
mode = 'RO',
units = 'V',
typeStr = "Float32",
disp = '{:1.3f}',
linkedGet = lambda read: self.READ_VOUT.get(read=read)*0.5E-3, # Conversion factor: 0.5mV/Bit
dependencies = [self.READ_VOUT],
))

self.add(pr.LinkVariable(
name = 'Iout',
mode = 'RO',
units = 'A',
typeStr = "Float32",
disp = '{:1.3f}',
linkedGet = lambda read: self.READ_IOUT.get(read=read)*10.0E-3, # Conversion factor: 10mA/Bit
dependencies = [self.READ_IOUT],
))

self.add(pr.LinkVariable(
name = "DieTempature",
mode = 'RO',
linkedGet = lambda read: self.READ_TEMPERATURE_1.get(read=read)*1.0, # Conversion factor: 1 degC/Bit
typeStr = "Float32",
disp = '{:1.3f}',
units = 'degC',
dependencies = [self.READ_TEMPERATURE_1],
))

self.add(pr.LinkVariable(
name = 'Pin',
description = 'Power Measurement',
mode = 'RO',
linkedGet = lambda read: (self.Vin.get(read=read))*(self.Iin.get(read=read)),
typeStr = "Float32",
disp = '{:1.3f}',
units = 'W',
dependencies = [self.Vin,self.Iin],
))

self.add(pr.LinkVariable(
name = 'Pout',
description = 'Power Measurement',
mode = 'RO',
linkedGet = lambda read: (self.Vout.get(read=read))*(self.Iout.get(read=read)),
typeStr = "Float32",
disp = '{:1.3f}',
units = 'W',
dependencies = [self.Vout,self.Iout],
))

self.add(pr.LinkVariable(
name = 'Peff',
description = 'Power Conversion Efficiency',
mode = 'RO',
linkedGet = lambda read: 100.0*(self.Pout.get(read=read))/(self.Pin.get(read=read)) if self.Pin.get(read=read)>0.0 else 0.0,
typeStr = "Float32",
disp = '{:1.1f}',
units = '%',
dependencies = [self.Pin,self.Pout],
))
8 changes: 4 additions & 4 deletions python/surf/devices/linear/_Ltc4151.py
Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,7 @@ def __init__(self,
units = 'A',
disp = '{:1.3f}',
dependencies = [self.SenseMsb,self.SenseLsb],
linkedGet = lambda: (int(self.SenseMsb.value()<<4)|int(self.SenseLsb.value()&0xF))*20.0E-6/self.senseRes
linkedGet = lambda read: (int(self.SenseMsb.get(read=read)<<4)|int(self.SenseLsb.get(read=read)&0xF))*20.0E-6/self.senseRes
))

self.add(pr.RemoteVariable(
Expand Down Expand Up @@ -90,7 +90,7 @@ def __init__(self,
units = 'V',
disp = '{:1.3f}',
dependencies = [self.VinMsb,self.VinLsb],
linkedGet = lambda: (int(self.VinMsb.value()<<4)|int(self.VinLsb.value()&0xF))*25.0E-3
linkedGet = lambda read: (int(self.VinMsb.get(read=read)<<4)|int(self.VinLsb.get(read=read)&0xF))*25.0E-3
))

self.add(pr.LinkVariable(
Expand All @@ -100,7 +100,7 @@ def __init__(self,
units = 'W',
disp = '{:1.3f}',
dependencies = [self.Vin,self.Iin],
linkedGet = lambda: (self.Vin.value())*(self.Iin.value())
linkedGet = lambda read: (self.Vin.get(read=read))*(self.Iin.get(read=read))
))

self.add(pr.RemoteVariable(
Expand Down Expand Up @@ -134,7 +134,7 @@ def __init__(self,
units = 'V',
disp = '{:1.3f}',
dependencies = [self.AdinMsb,self.AdinLsb],
linkedGet = lambda: (int(self.AdinMsb.value()<<4)|int(self.AdinLsb.value()&0xF))*500.0E-6
linkedGet = lambda read: (int(self.AdinMsb.get(read=read)<<4)|int(self.AdinLsb.get(read=read)&0xF))*500.0E-6
))

self.add(pr.RemoteVariable(
Expand Down
1 change: 1 addition & 0 deletions python/surf/devices/linear/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -9,4 +9,5 @@
##############################################################################
from surf.devices.linear._Ltc2270 import *
from surf.devices.linear._Ltc2945 import *
from surf.devices.linear._Ltc3815 import *
from surf.devices.linear._Ltc4151 import *
1 change: 1 addition & 0 deletions python/surf/devices/micron/_AxiMicronMt28ew.py
Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,7 @@ def __init__(self,
bulkOpEn = False,
hidden = True,
verify = False,
groups = ['NoStream','NoState','NoConfig'], # Not saving config/state to YAML
))

self.add(pr.LocalCommand(
Expand Down
1 change: 1 addition & 0 deletions python/surf/devices/micron/_AxiMicronN25Q.py
Original file line number Diff line number Diff line change
Expand Up @@ -107,6 +107,7 @@ def __init__(self,
bulkOpEn = False,
hidden = True,
verify = False,
groups = ['NoStream','NoState','NoConfig'], # Not saving config/state to YAML
))

##############################
Expand Down
1 change: 1 addition & 0 deletions python/surf/devices/micron/_AxiMicronP30.py
Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,7 @@ def __init__(self,
bulkOpEn = False,
hidden = True,
verify = False,
groups = ['NoStream','NoState','NoConfig'], # Not saving config/state to YAML
))

self.add(pr.LocalCommand(
Expand Down
7 changes: 6 additions & 1 deletion python/surf/devices/nxp/_Sa56004x.py
Original file line number Diff line number Diff line change
Expand Up @@ -18,9 +18,14 @@
class Sa56004x(pr.Device):
def __init__(self,
pollInterval = 1,
simpleViewList = ['enable', 'LocalTemperature', 'RemoteTemperature', 'RemoteTcritSetpoint'],
**kwargs):
super().__init__(**kwargs)

if simpleViewList is not None:
self.simpleViewList = simpleViewList[:]
self.simpleViewList.append('enable')

############################################################################

def getTempReg(var):
Expand Down Expand Up @@ -560,5 +565,5 @@ def simpleView(self):
# Hide all the variable
self.hideVariables(hidden=True)
# Then unhide the most interesting ones
vars = ['enable', 'LocalTemperature', 'RemoteTemperature']
vars = self.simpleViewList
self.hideVariables(hidden=False, variables=vars)
1 change: 1 addition & 0 deletions python/surf/devices/silabs/_Si5324.py
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@ def __init__(self,**kwargs):
hidden = True,
base = pr.UInt,
mode = "RW",
groups = ['NoStream','NoState','NoConfig'], # Not saving config/state to YAML
))

self.add(pr.LocalVariable(
Expand Down
1 change: 1 addition & 0 deletions python/surf/devices/silabs/_Si5326.py
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@ def __init__(self,**kwargs):
hidden = True,
base = pr.UInt,
mode = "RW",
groups = ['NoStream','NoState','NoConfig'], # Not saving config/state to YAML
))

self.add(pr.LocalVariable(
Expand Down
1 change: 1 addition & 0 deletions python/surf/devices/silabs/_Si5345Pages.py
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ def __init__(self,
hidden = True,
base = pr.UInt,
mode = "RW",
groups = ['NoStream','NoState','NoConfig'], # Not saving config/state to YAML
))

def MyLinkVariable(self, name, description, offset, bitSize, mode, bitOffset=0, pollInterval=0, value=None, hidden=False):
Expand Down
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