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Merge pull request #387 from slaclab/pre-release
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v1.9.7 release candidate
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@ruck314
ruck314 authored Mar 5, 2019
2 parents cfcc587 + bb7b03b commit aab96e9
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Showing 29 changed files with 899 additions and 851 deletions.
20 changes: 14 additions & 6 deletions axi/axi-lite/rtl/AxiLiteCrossbar.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -171,9 +171,13 @@ begin

for m in MASTERS_CONFIG_G'range loop
-- Check for address match
if (sAxiWriteMasters(s).awaddr(31 downto MASTERS_CONFIG_G(m).addrBits) =
MASTERS_CONFIG_G(m).baseAddr(31 downto MASTERS_CONFIG_G(m).addrBits) and
MASTERS_CONFIG_G(m).connectivity(s) = '1') then
if (
StdMatch( -- Use std_match to allow dontcares ('-')
sAxiWriteMasters(s).awaddr(31 downto MASTERS_CONFIG_G(m).addrBits),
MASTERS_CONFIG_G(m).baseAddr(31 downto MASTERS_CONFIG_G(m).addrBits))
and (
MASTERS_CONFIG_G(m).connectivity(s) = '1'))
then
v.slave(s).wrReqs(m) := '1';
v.slave(s).wrReqNum := conv_std_logic_vector(m, REQ_NUM_SIZE_C);
-- print("AxiLiteCrossbar: Slave " & str(s) & " reqd Master " & str(m) & " Write addr " & hstr(sAxiWriteMasters(s).awaddr));
Expand Down Expand Up @@ -235,9 +239,13 @@ begin
if (sAxiReadMasters(s).arvalid = '1') then
for m in MASTERS_CONFIG_G'range loop
-- Check for address match
if (sAxiReadMasters(s).araddr(31 downto MASTERS_CONFIG_G(m).addrBits) =
MASTERS_CONFIG_G(m).baseAddr(31 downto MASTERS_CONFIG_G(m).addrBits) and
MASTERS_CONFIG_G(m).connectivity(s) = '1') then
if (
StdMatch( -- Use std_match to allow dontcares ('-')
sAxiReadMasters(s).araddr(31 downto MASTERS_CONFIG_G(m).addrBits),
MASTERS_CONFIG_G(m).baseAddr(31 downto MASTERS_CONFIG_G(m).addrBits))
and (
MASTERS_CONFIG_G(m).connectivity(s) = '1'))
then
v.slave(s).rdReqs(m) := '1';
v.slave(s).rdReqNum := conv_std_logic_vector(m, REQ_NUM_SIZE_C);
end if;
Expand Down
74 changes: 38 additions & 36 deletions axi/axi-lite/rtl/AxiVersion.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -24,20 +24,20 @@ use work.AxiLitePkg.all;

entity AxiVersion is
generic (
TPD_G : time := 1 ns;
TPD_G : time := 1 ns;
BUILD_INFO_G : BuildInfoType;
SIM_DNA_VALUE_G : slv := X"000000000000000000000000";
DEVICE_ID_G : slv(31 downto 0) := (others => '0');
CLK_PERIOD_G : real := 8.0E-9; -- units of seconds
XIL_DEVICE_G : string := "7SERIES"; -- Either "7SERIES" or "ULTRASCALE"
EN_DEVICE_DNA_G : boolean := false;
EN_DS2411_G : boolean := false;
EN_ICAP_G : boolean := false;
USE_SLOWCLK_G : boolean := false;
BUFR_CLK_DIV_G : positive := 8;
AUTO_RELOAD_EN_G : boolean := false;
AUTO_RELOAD_TIME_G : real range 0.0 to 30.0 := 10.0; -- units of seconds
AUTO_RELOAD_ADDR_G : slv(31 downto 0) := (others => '0'));
SIM_DNA_VALUE_G : slv := X"000000000000000000000000";
DEVICE_ID_G : slv(31 downto 0) := (others => '0');
CLK_PERIOD_G : real := 8.0E-9; -- units of seconds
XIL_DEVICE_G : string := "7SERIES"; -- Either "7SERIES" or "ULTRASCALE"
EN_DEVICE_DNA_G : boolean := false;
EN_DS2411_G : boolean := false;
EN_ICAP_G : boolean := false;
USE_SLOWCLK_G : boolean := false;
BUFR_CLK_DIV_G : positive := 8;
AUTO_RELOAD_EN_G : boolean := false;
AUTO_RELOAD_TIME_G : positive := 10; -- units of seconds
AUTO_RELOAD_ADDR_G : slv(31 downto 0) := (others => '0'));
port (
-- AXI-Lite Interface
axiClk : in sl;
Expand Down Expand Up @@ -65,7 +65,6 @@ end AxiVersion;

architecture rtl of AxiVersion is

constant RELOAD_COUNT_C : integer := integer(AUTO_RELOAD_TIME_G / CLK_PERIOD_G);
constant TIMEOUT_1HZ_C : natural := (getTimeRatio(1.0, CLK_PERIOD_G) -1);
constant COUNTER_ZERO_C : slv(31 downto 0) := X"00000000";

Expand All @@ -76,8 +75,7 @@ architecture rtl of AxiVersion is
upTimeCnt : slv(31 downto 0);
timer : natural range 0 to TIMEOUT_1HZ_C;
scratchPad : slv(31 downto 0);
counter : slv(31 downto 0);
counterRst : sl;
reloadTimer : natural range 0 to AUTO_RELOAD_TIME_G;
userReset : sl;
fpgaReload : sl;
haltReload : sl;
Expand All @@ -90,8 +88,7 @@ architecture rtl of AxiVersion is
upTimeCnt => (others => '0'),
timer => 0,
scratchPad => (others => '0'),
counter => (others => '0'),
counterRst => '0',
reloadTimer => 0,
userReset => '0',
fpgaReload => '0',
haltReload => '0',
Expand All @@ -102,8 +99,8 @@ architecture rtl of AxiVersion is
signal r : RegType := REG_INIT_C;
signal rin : RegType;

signal dnaValue : slv(127 downto 0) := (others => '0');
signal fdValue : slv(63 downto 0) := (others => '0');
signal dnaValue : slv(127 downto 0) := (others => '0');
signal fdValue : slv(63 downto 0) := (others => '0');

attribute rom_style : string;
attribute rom_style of BUILD_STRING_ROM_C : constant is "distributed";
Expand Down Expand Up @@ -167,19 +164,6 @@ begin
-- Latch the current value
v := r;

---------------------------------
-- First Stage Boot Loader (FSBL)
---------------------------------
-- Check if timer enabled
if fpgaEnReload = '1' then
v.counter := v.counter + 1;
end if;

-- Check for reload condition
if AUTO_RELOAD_EN_G and (r.counter = RELOAD_COUNT_C) and (fpgaEnReload = '1') and (r.haltReload = '0') then
v.fpgaReload := '1';
end if;

------------------------
-- AXI-Lite Transactions
------------------------
Expand All @@ -199,20 +183,38 @@ begin
axiSlaveRegisterR(axilEp, x"300", 0, fdValue);
axiSlaveRegisterR(axilEp, x"400", userValues);
axiSlaveRegisterR(axilEp, x"500", 0, DEVICE_ID_G);

axiSlaveRegisterR(axilEp, x"600", 0, BUILD_INFO_C.gitHash);

axiSlaveRegisterR(axilEp, x"700", 0, dnaValue);
axiSlaveRegisterR(axilEp, x"800", BUILD_STRING_ROM_C);

-- Close the transaction
axiSlaveDefault(axilEp, v.axiWriteSlave, v.axiReadSlave, AXI_RESP_DECERR_C);

---------------------------------
-- Uptime counter
---------------------------------
if r.timer = TIMEOUT_1HZ_C then
v.timer := 0;
-- Reset the counter
v.timer := 0;

-- Increment the Counter
v.upTimeCnt := r.upTimeCnt + 1;

---------------------------------
-- First Stage Boot Loader (FSBL)
---------------------------------
-- Check if timer enabled
if (fpgaEnReload = '1') and (r.reloadTimer /= AUTO_RELOAD_TIME_G) then
v.reloadTimer := r.reloadTimer + 1;
end if;

-- Check for reload condition
if AUTO_RELOAD_EN_G and (r.reloadTimer = AUTO_RELOAD_TIME_G) and (fpgaEnReload = '1') and (r.haltReload = '0') then
v.fpgaReload := '1';
end if;

else
v.timer := r.timer + 1;
end if;
Expand Down
73 changes: 37 additions & 36 deletions axi/axi-lite/rtl/AxiVersionLegacy.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,20 +24,20 @@ use work.AxiLitePkg.all;

entity AxiVersionLegacy is
generic (
TPD_G : time := 1 ns;
TPD_G : time := 1 ns;
BUILD_INFO_G : BuildInfoType;
SIM_DNA_VALUE_G : slv := X"000000000000000000000000";
DEVICE_ID_G : slv(31 downto 0) := (others => '0');
CLK_PERIOD_G : real := 8.0E-9; -- units of seconds
XIL_DEVICE_G : string := "7SERIES"; -- Either "7SERIES" or "ULTRASCALE"
EN_DEVICE_DNA_G : boolean := false;
EN_DS2411_G : boolean := false;
EN_ICAP_G : boolean := false;
USE_SLOWCLK_G : boolean := false;
BUFR_CLK_DIV_G : positive := 8;
AUTO_RELOAD_EN_G : boolean := false;
AUTO_RELOAD_TIME_G : real range 0.0 to 30.0 := 10.0; -- units of seconds
AUTO_RELOAD_ADDR_G : slv(31 downto 0) := (others => '0'));
SIM_DNA_VALUE_G : slv := X"000000000000000000000000";
DEVICE_ID_G : slv(31 downto 0) := (others => '0');
CLK_PERIOD_G : real := 8.0E-9; -- units of seconds
XIL_DEVICE_G : string := "7SERIES"; -- Either "7SERIES" or "ULTRASCALE"
EN_DEVICE_DNA_G : boolean := false;
EN_DS2411_G : boolean := false;
EN_ICAP_G : boolean := false;
USE_SLOWCLK_G : boolean := false;
BUFR_CLK_DIV_G : positive := 8;
AUTO_RELOAD_EN_G : boolean := false;
AUTO_RELOAD_TIME_G : positive := 10; -- units of seconds
AUTO_RELOAD_ADDR_G : slv(31 downto 0) := (others => '0'));
port (
-- AXI-Lite Interface
axiClk : in sl;
Expand Down Expand Up @@ -65,7 +65,6 @@ end AxiVersionLegacy;

architecture rtl of AxiVersionLegacy is

constant RELOAD_COUNT_C : integer := integer(AUTO_RELOAD_TIME_G / CLK_PERIOD_G);
constant TIMEOUT_1HZ_C : natural := (getTimeRatio(1.0, CLK_PERIOD_G) -1);
constant COUNTER_ZERO_C : slv(31 downto 0) := X"00000000";

Expand All @@ -76,8 +75,7 @@ architecture rtl of AxiVersionLegacy is
upTimeCnt : slv(31 downto 0);
timer : natural range 0 to TIMEOUT_1HZ_C;
scratchPad : slv(31 downto 0);
counter : slv(31 downto 0);
counterRst : sl;
reloadTimer : natural range 0 to AUTO_RELOAD_TIME_G;
userReset : sl;
fpgaReload : sl;
haltReload : sl;
Expand All @@ -90,8 +88,7 @@ architecture rtl of AxiVersionLegacy is
upTimeCnt => (others => '0'),
timer => 0,
scratchPad => (others => '0'),
counter => (others => '0'),
counterRst => '0',
reloadTimer => 0,
userReset => '1', -- Asserted on powerup
fpgaReload => '0',
haltReload => '0',
Expand Down Expand Up @@ -159,31 +156,17 @@ begin
bootAddress => r.fpgaReloadAddr);
end generate;

comb : process (axiReadMaster, axiRst, axiWriteMaster, dnaValue, fdValue, fpgaEnReload, r,
userValues) is
comb : process (axiReadMaster, axiRst, axiWriteMaster, dnaValue, fdValue,
fpgaEnReload, r, userValues) is
variable v : RegType;
variable axilEp : AxiLiteEndpointType;
begin
-- Latch the current value
v := r;

---------------------------------
-- First Stage Boot Loader (FSBL)
---------------------------------
-- Check if timer enabled
if fpgaEnReload = '1' then
v.counter := v.counter + 1;
end if;

-- Check for reload condition
if AUTO_RELOAD_EN_G and (r.counter = RELOAD_COUNT_C) and (fpgaEnReload = '1') and (r.haltReload = '0') then
v.fpgaReload := '1';
end if;

------------------------
-- AXI-Lite Transactions
------------------------
------------------------

-- Determine the transaction type
axiSlaveWaitTxn(axilEp, axiWriteMaster, axiReadMaster, v.axiWriteSlave, v.axiReadSlave);
Expand All @@ -196,7 +179,7 @@ begin

axiSlaveRegister(axilEp, X"01C", 0, v.fpgaReload);
axiSlaveRegister(axilEp, X"020", 0, v.fpgaReloadAddr);
axiSlaveRegister(axilEp, X"024", 0, v.counter, COUNTER_ZERO_C);
axiSlaveRegister(axilEp, X"024", 0, v.reloadTimer, COUNTER_ZERO_C);
axiSlaveRegister(axilEp, X"028", 0, v.haltReload);
axiSlaveRegisterR(axilEp, X"02C", 0, r.upTimeCnt);
axiSlaveRegisterR(axilEp, X"030", 0, DEVICE_ID_G);
Expand All @@ -206,14 +189,32 @@ begin
axiSlaveRegisterR(axilEp, X"400", userValues);
axiSlaveRegisterR(axilEp, X"800", BUILD_STRING_ROM_C);

-- Close the transaction
axiSlaveDefault(axilEp, v.axiWriteSlave, v.axiReadSlave, AXI_RESP_DECERR_C);

---------------------------------
-- Uptime counter
---------------------------------
if r.timer = TIMEOUT_1HZ_C then
v.timer := 0;
-- Reset the counter
v.timer := 0;

-- Increment the Counter
v.upTimeCnt := r.upTimeCnt + 1;

---------------------------------
-- First Stage Boot Loader (FSBL)
---------------------------------
-- Check if timer enabled
if (fpgaEnReload = '1') and (r.reloadTimer /= AUTO_RELOAD_TIME_G) then
v.reloadTimer := r.reloadTimer + 1;
end if;

-- Check for reload condition
if AUTO_RELOAD_EN_G and (r.reloadTimer = AUTO_RELOAD_TIME_G) and (fpgaEnReload = '1') and (r.haltReload = '0') then
v.fpgaReload := '1';
end if;

else
v.timer := r.timer + 1;
end if;
Expand Down
14 changes: 7 additions & 7 deletions axi/axi-stream/rtl/AxiStreamDeMux.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,13 +24,13 @@ use work.AxiStreamPkg.all;

entity AxiStreamDeMux is
generic (
TPD_G : time := 1 ns;
NUM_MASTERS_G : integer range 1 to 32 := 12;
MODE_G : string := "INDEXED"; -- Or "ROUTED"
TDEST_ROUTES_G : slv8Array := (0 => "--------"); -- Only used in ROUTED mode
PIPE_STAGES_G : integer range 0 to 16 := 0;
TDEST_HIGH_G : integer range 0 to 7 := 7;
TDEST_LOW_G : integer range 0 to 7 := 0);
TPD_G : time := 1 ns;
NUM_MASTERS_G : integer range 1 to 256 := 12;
MODE_G : string := "INDEXED"; -- Or "ROUTED"
TDEST_ROUTES_G : slv8Array := (0 => "--------"); -- Only used in ROUTED mode
PIPE_STAGES_G : integer range 0 to 16 := 0;
TDEST_HIGH_G : integer range 0 to 7 := 7;
TDEST_LOW_G : integer range 0 to 7 := 0);
port (
-- Clock and reset
axisClk : in sl;
Expand Down
22 changes: 11 additions & 11 deletions axi/axi-stream/rtl/AxiStreamMux.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,29 +26,29 @@ use work.AxiStreamPkg.all;

entity AxiStreamMux is
generic (
TPD_G : time := 1 ns;
PIPE_STAGES_G : integer range 0 to 16 := 0;
NUM_SLAVES_G : integer range 1 to 32 := 4;
TPD_G : time := 1 ns;
PIPE_STAGES_G : integer range 0 to 16 := 0;
NUM_SLAVES_G : integer range 1 to 256 := 4;
-- In INDEXED mode, the output TDEST is set based on the selected slave index
-- In ROUTED mode, TDEST is set accoring to the TDEST_ROUTES_G table
MODE_G : string := "INDEXED";
MODE_G : string := "INDEXED";
-- In ROUTED mode, an array mapping how TDEST should be assigned for each slave port
-- Each TDEST bit can be set to '0', '1' or '-' for passthrough from slave TDEST.
TDEST_ROUTES_G : Slv8Array := (0 => "--------");
TDEST_ROUTES_G : Slv8Array := (0 => "--------");
-- In INDEXED mode, assign slave index to TDEST at this bit offset
TDEST_LOW_G : integer range 0 to 7 := 0;
TDEST_LOW_G : integer range 0 to 7 := 0;
-- Set to true if interleaving dests
ILEAVE_EN_G : boolean := false;
ILEAVE_EN_G : boolean := false;
-- Rearbitrate when tValid drops on selected channel, ignored when ILEAVE_EN_G=false
ILEAVE_ON_NOTVALID_G : boolean := false;
ILEAVE_ON_NOTVALID_G : boolean := false;
-- Max number of transactions between arbitrations, 0 = unlimited, ignored when ILEAVE_EN_G=false
ILEAVE_REARB_G : natural := 0;
ILEAVE_REARB_G : natural := 0;
-- One cycle gap in stream between during rearbitration.
-- Set true for better timing, false for higher throughput.
REARB_DELAY_G : boolean := true;
REARB_DELAY_G : boolean := true;
-- Block selected slave txns arriving on same cycle as rearbitrate or disableSel from going through,
-- creating 1 cycle gap. This might be needed logically but decreases throughput.
FORCED_REARB_HOLD_G : boolean := false);
FORCED_REARB_HOLD_G : boolean := false);

port (
-- Clock and reset
Expand Down
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