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Merge pull request #348 from slaclab/pre-release
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v1.9.3 release candidate
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@ruck314
ruck314 authored Nov 29, 2018
2 parents 2fbb06e + a5c59d8 commit b156326
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Showing 5 changed files with 48 additions and 49 deletions.
2 changes: 1 addition & 1 deletion axi/axi4/rtl/AxiRam.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -378,7 +378,7 @@ begin
if (READ_LATENCY_G = 0) then
rdEn <= "11";
else
rdEn <= r.rdEn;
rdEn <= v.rdEn;
end if;

--------------------------
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17 changes: 7 additions & 10 deletions axi/dma/rtl/AxiStreamDmaV2Desc.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,6 @@ architecture rtl of AxiStreamDmaV2Desc is
axiWriteMaster : AxiWriteMasterType;

-- Configuration
buffBaseAddr : slv(31 downto 0); -- For buffer entries
wrBaseAddr : slv(63 downto 0); -- For wr ring buffer
rdBaseAddr : slv(63 downto 0); -- For rd ring buffer
maxSize : slv(31 downto 0);
Expand Down Expand Up @@ -202,7 +201,6 @@ architecture rtl of AxiStreamDmaV2Desc is
axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C,
axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C,
axiWriteMaster => axiWriteMasterInit(AXI_CONFIG_G, '1', "01", "0000"),
buffBaseAddr => (others => '0'),
wrBaseAddr => (others => '0'),
rdBaseAddr => (others => '0'),
maxSize => (others => '0'),
Expand Down Expand Up @@ -472,7 +470,6 @@ begin
axiSlaveRegister(regCon, x"018", 0, v.rdBaseAddr(31 downto 0));
axiSlaveRegister(regCon, x"01C", 0, v.rdBaseAddr(63 downto 32));
axiSlaveRegister(regCon, x"020", 0, v.fifoReset);
axiSlaveRegister(regCon, x"024", 0, v.buffBaseAddr);
axiSlaveRegister(regCon, x"028", 0, v.maxSize);
axiSlaveRegister(regCon, x"02C", 0, v.online);
axiSlaveRegister(regCon, x"030", 0, v.acknowledge);
Expand Down Expand Up @@ -506,7 +503,7 @@ begin

if DESC_128_EN_C then
axiSlaveRegister(regCon, x"060", 0, v.fifoDin);
axiWrDetect(regCon, x"064", v.rdFifoWr(2));
axiWrDetect(regCon, x"060", v.rdFifoWr(2));

axiSlaveRegister(regCon, x"064", 0, v.fifoDin);
axiWrDetect(regCon, x"064", v.rdFifoWr(3));
Expand Down Expand Up @@ -604,11 +601,11 @@ begin
for i in 0 to CHAN_COUNT_G-1 loop

if DESC_128_EN_C then
v.dmaWrDescAck(i).address(63 downto 40) := r.buffBaseAddr(31 downto 8);
v.dmaWrDescAck(i).address(63 downto 40) := (others=>'0');
v.dmaWrDescAck(i).address(39 downto 4) := wrFifoDout(63 downto 28);
v.dmaWrDescAck(i).address(3 downto 0) := (others=>'0');
else
v.dmaWrDescAck(i).address(63 downto 32) := r.buffBaseAddr;
v.dmaWrDescAck(i).address(63 downto 32) := (others=>'0');
v.dmaWrDescAck(i).address(31 downto 0) := r.wrAddr;
end if;

Expand Down Expand Up @@ -774,9 +771,9 @@ begin
if DESC_128_EN_C then
v.axiWriteMaster.wdata(127) := '1';
v.axiWriteMaster.wdata(126 downto 64) := (others => '0');
v.axiWriteMaster.wdata(63 downto 32) := dmaWrDescRet(descIndex).buffId;
v.axiWriteMaster.wdata(63 downto 32) := dmaRdDescRet(descIndex).buffId;
v.axiWriteMaster.wdata(31 downto 3) := (others => '0');
v.axiWriteMaster.wdata(2 downto 0) := dmaWrDescRet(descIndex).result;
v.axiWriteMaster.wdata(2 downto 0) := dmaRdDescRet(descIndex).result;

v.axiWriteMaster.wstrb := resize(x"FFFF", 128);

Expand Down Expand Up @@ -876,7 +873,7 @@ begin

-- Format request, 128-bits
if DESC_128_EN_C then
dmaRdReq.address(63 downto 40) := r.buffBaseAddr(31 downto 8);
dmaRdReq.address(63 downto 40) := (others=>'0');
dmaRdReq.address(39 downto 4) := rdFifoDout(127 downto 92);
dmaRdReq.address(3 downto 0) := (others=>'0');
dmaRdReq.buffId(27 downto 0) := rdFifoDout(91 downto 64);
Expand All @@ -890,7 +887,7 @@ begin

-- Format request, 64-bits
else
dmaRdReq.address(63 downto 32) := r.buffBaseAddr;
dmaRdReq.address(63 downto 32) := (others=>'0');
dmaRdReq.address(31 downto 0) := r.rdAddr;
dmaRdReq.dest := rdFifoDout(63 downto 56);
dmaRdReq.size(23 downto 0) := rdFifoDout(55 downto 32);
Expand Down
40 changes: 20 additions & 20 deletions protocols/packetizer/rtl/AxiStreamPacketizer.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -27,20 +27,20 @@ use work.SsiPkg.all;
entity AxiStreamPacketizer is

generic (
TPD_G : time := 1 ns;
MAX_PACKET_BYTES_G : integer := 1440; -- Must be a multiple of 8
MIN_TKEEP_G : slv(7 downto 0) := x"01";
OUTPUT_SSI_G : boolean := true; -- SSI compliant output (SOF on tuser)
INPUT_PIPE_STAGES_G : integer := 0;
OUTPUT_PIPE_STAGES_G : integer := 0);
TPD_G : time := 1 ns;
MAX_PACKET_BYTES_G : integer := 1440; -- Must be a multiple of 8
MIN_TKEEP_G : slv(7 downto 0) := x"01";
OUTPUT_SSI_G : boolean := true; -- SSI compliant output (SOF on tuser)
INPUT_PIPE_STAGES_G : integer := 0;
OUTPUT_PIPE_STAGES_G : integer := 0);

port (
-- AXI-Lite Interface for local registers
axisClk : in sl;
axisRst : in sl;

-- Actual byte count; will be truncated to multiple of word-size
maxPktBytes : in slv(bitSize(MAX_PACKET_BYTES_G) - 1 downto 0) := toSlv(MAX_PACKET_BYTES_G, bitSize(MAX_PACKET_BYTES_G));
maxPktBytes : in slv(bitSize(MAX_PACKET_BYTES_G) - 1 downto 0) := toSlv(MAX_PACKET_BYTES_G, bitSize(MAX_PACKET_BYTES_G));

sAxisMaster : in AxiStreamMasterType;
sAxisSlave : out AxiStreamSlaveType;
Expand All @@ -52,12 +52,12 @@ end entity AxiStreamPacketizer;

architecture rtl of AxiStreamPacketizer is

constant LD_WORD_SIZE_C : positive := 3;
constant WORD_SIZE_C : positive := 2**LD_WORD_SIZE_C;
constant LD_WORD_SIZE_C : positive := 3;
constant WORD_SIZE_C : positive := 2**LD_WORD_SIZE_C;

subtype WordCounterType is unsigned(maxPktBytes'left - LD_WORD_SIZE_C downto 0);
subtype WordCounterType is unsigned(maxPktBytes'left - LD_WORD_SIZE_C downto 0);

constant PROTO_WORDS_C : positive := 3;
constant PROTO_WORDS_C : positive := 3;
constant MAX_WORD_COUNT_C : WordCounterType := to_unsigned(MAX_PACKET_BYTES_G / WORD_SIZE_C, WordCounterType'length);

constant AXIS_CONFIG_C : AxiStreamConfigType := (
Expand Down Expand Up @@ -93,7 +93,7 @@ architecture rtl of AxiStreamPacketizer is
frameNumber => (others => '0'),
packetNumber => (others => '0'),
wordCount => (others => '0'),
maxWords => (0 => '1', others => '0'),
maxWords => to_unsigned(1, WordCounterType'length),
eof => '0',
tUserLast => (others => '0'),
inputAxisSlave => AXI_STREAM_SLAVE_INIT_C,
Expand All @@ -107,7 +107,7 @@ architecture rtl of AxiStreamPacketizer is
signal outputAxisMaster : AxiStreamMasterType;
signal outputAxisSlave : AxiStreamSlaveType;

signal maxWords : WordCounterType;
signal maxWords : WordCounterType;
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "TRUE";
-- attribute dont_touch of inputAxisMaster : signal is "TRUE";
Expand Down Expand Up @@ -163,11 +163,11 @@ begin
-- NOTE: wordCount is compared only after incrementing
-- (and doing some work in MOVE_S), thus at least
-- one non-protocol word must fit.
if ( maxWords <= to_unsigned(PROTO_WORDS_C, maxWords'length) ) then
if (maxWords <= to_unsigned(PROTO_WORDS_C, maxWords'length)) then
fits := false;
else
fits := true;
if ( maxWords >= MAX_WORD_COUNT_C ) then
if (maxWords >= MAX_WORD_COUNT_C) then
v.maxWords := MAX_WORD_COUNT_C - PROTO_WORDS_C;
else
v.maxWords := maxWords - PROTO_WORDS_C;
Expand Down Expand Up @@ -209,7 +209,7 @@ begin
v.outputAxisMaster.tUser := (others => '0');
v.outputAxisMaster.tDest := (others => '0');
v.outputAxisMaster.tId := (others => '0');
v.outputAxisMaster.tKeep := resize(x"00FF",AXI_STREAM_MAX_TKEEP_WIDTH_C);
v.outputAxisMaster.tKeep := resize(x"00FF", AXI_STREAM_MAX_TKEEP_WIDTH_C);

-- Increment word count with each txn
v.wordCount := r.wordCount + 1;
Expand Down Expand Up @@ -262,13 +262,13 @@ begin
-- No room for TAIL this cycle and will add it in the next state
v.outputAxisMaster.tKeep(7 downto 0) := (x"FF" or MIN_TKEEP_G);
-- Save the tUser at tLast
v.tUserLast := inputAxisMaster.tUser(7 downto 0);
v.tUserLast := inputAxisMaster.tUser(7 downto 0);
-- Set the flag
v.eof := '1';
v.eof := '1';
-- Reset the flag
v.outputAxisMaster.tLast := '0';
v.outputAxisMaster.tLast := '0';
-- Next state
v.state := TAIL_S;
v.state := TAIL_S;
end case;
----------------------------------------------------------------------

Expand Down
28 changes: 14 additions & 14 deletions protocols/packetizer/rtl/AxiStreamPacketizer2.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ entity AxiStreamPacketizer2 is
BRAM_EN_G : boolean := false;
CRC_MODE_G : string := "DATA"; -- or "NONE" or "FULL"
CRC_POLY_G : slv(31 downto 0) := x"04C11DB7";
MAX_PACKET_BYTES_G : positive := 256*8; -- Must be a multiple of 8
MAX_PACKET_BYTES_G : positive := 256*8; -- Must be a multiple of 8
TDEST_BITS_G : natural := 8;
INPUT_PIPE_STAGES_G : natural := 0;
OUTPUT_PIPE_STAGES_G : natural := 0);
Expand All @@ -52,16 +52,16 @@ end entity AxiStreamPacketizer2;
architecture rtl of AxiStreamPacketizer2 is


constant LD_WORD_SIZE_C : positive := 3;
constant WORD_SIZE_C : positive := 2**LD_WORD_SIZE_C;
constant LD_WORD_SIZE_C : positive := 3;
constant WORD_SIZE_C : positive := 2**LD_WORD_SIZE_C;

subtype WordCounterType is unsigned(maxPktBytes'left - LD_WORD_SIZE_C downto 0);
subtype WordCounterType is unsigned(maxPktBytes'left - LD_WORD_SIZE_C downto 0);

constant PROTO_WORDS_C : positive := 3;
constant PROTO_WORDS_C : positive := 3;
constant MAX_WORD_COUNT_C : WordCounterType := to_unsigned(MAX_PACKET_BYTES_G / WORD_SIZE_C, WordCounterType'length);
constant CRC_EN_C : boolean := (CRC_MODE_G /= "NONE");
constant CRC_HEAD_TAIL_C : boolean := (CRC_MODE_G = "FULL");
constant ADDR_WIDTH_C : positive := ite((TDEST_BITS_G = 0), 1, TDEST_BITS_G);
constant CRC_EN_C : boolean := (CRC_MODE_G /= "NONE");
constant CRC_HEAD_TAIL_C : boolean := (CRC_MODE_G = "FULL");
constant ADDR_WIDTH_C : positive := ite((TDEST_BITS_G = 0), 1, TDEST_BITS_G);

type StateType is (
IDLE_S,
Expand Down Expand Up @@ -99,7 +99,7 @@ architecture rtl of AxiStreamPacketizer2 is
activeTDest => (others => '0'),
ramWe => '0',
wordCount => (others => '0'),
maxWords => (0 => '1', others => '0'),
maxWords => to_unsigned(1, WordCounterType'length),
eof => '0',
lastByteCount => "1000",
tUserLast => (others => '0'),
Expand Down Expand Up @@ -131,7 +131,7 @@ architecture rtl of AxiStreamPacketizer2 is
signal crcOut : slv(31 downto 0) := (others => '0');
signal crcRem : slv(31 downto 0) := (others => '1');

signal maxWords : WordCounterType;
signal maxWords : WordCounterType;

-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "TRUE";
Expand Down Expand Up @@ -297,11 +297,11 @@ begin
-- NOTE: wordCount is compared only after incrementing
-- (and doing some work in MOVE_S), thus at least
-- one non-protocol word must fit.
if ( maxWords <= to_unsigned(PROTO_WORDS_C, maxWords'length) ) then
if (maxWords <= to_unsigned(PROTO_WORDS_C, maxWords'length)) then
fits := false;
else
fits := true;
if ( maxWords >= MAX_WORD_COUNT_C ) then
if (maxWords >= MAX_WORD_COUNT_C) then
v.maxWords := MAX_WORD_COUNT_C - PROTO_WORDS_C;
else
v.maxWords := maxWords - PROTO_WORDS_C;
Expand Down Expand Up @@ -382,7 +382,7 @@ begin
v.packetActive := '0';
v.tUserLast := inputAxisMaster.tUser(7 downto 0);
v.eof := '1';
v.lastByteCount := toSlv(getTKeep(inputAxisMaster.tKeep(7 downto 0),PACKETIZER2_AXIS_CFG_C), 4);
v.lastByteCount := toSlv(getTKeep(inputAxisMaster.tKeep(7 downto 0), PACKETIZER2_AXIS_CFG_C), 4);
v.outputAxisMaster.tLast := '0';
-- Next state
v.state := TAIL_S;
Expand Down Expand Up @@ -439,7 +439,7 @@ begin

-- Always a 64-bit transfer
v.outputAxisMaster.tKeep(7 downto 0) := x"FF";
v.outputAxisMaster.tStrb := v.outputAxisMaster.tKeep;
v.outputAxisMaster.tStrb := v.outputAxisMaster.tKeep;

if (r.state /= TAIL_S) then
v.crcIn := v.outputAxisMaster.tData(63 downto 0);
Expand Down
10 changes: 6 additions & 4 deletions xilinx/7Series/general/rtl/ClockManager7.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -33,11 +33,11 @@ entity ClockManager7 is
INPUT_BUFG_G : boolean := true;
FB_BUFG_G : boolean := true;
OUTPUT_BUFG_G : boolean := true;
RST_IN_POLARITY_G : sl := '1'; -- '0' for active low
RST_IN_POLARITY_G : sl := '1'; -- '0' for active low
NUM_CLOCKS_G : integer range 1 to 7;
-- MMCM attributes
BANDWIDTH_G : string := "OPTIMIZED";
CLKIN_PERIOD_G : real := 10.0; -- Input period in ns );
CLKIN_PERIOD_G : real := 10.0; -- Input period in ns );
DIVCLK_DIVIDE_G : integer range 1 to 106 := 1;
CLKFBOUT_MULT_F_G : real range 1.0 to 64.0 := 1.0;
CLKFBOUT_MULT_G : integer range 2 to 64 := 5;
Expand Down Expand Up @@ -379,8 +379,10 @@ begin
end generate OutBufgGen;

NoOutBufgGen : if (not OUTPUT_BUFG_G) generate
clkOutLoc <= clkOutMmcm;
clkOut <= clkOutLoc;
ClkOutGen : for i in NUM_CLOCKS_G-1 downto 0 generate
clkOutLoc(i) <= clkOutMmcm(i);
clkOut(i) <= clkOutLoc(i);
end generate ClkOutGen;
end generate NoOutBufgGen;

locked <= lockedLoc;
Expand Down

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