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Merge pull request #267 from slaclab/pre-release
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v1.8.9 release candidate
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@ruck314
ruck314 authored Aug 3, 2018
2 parents c4d7f2b + f48b56d commit f04df28
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Showing 9 changed files with 200 additions and 53 deletions.
71 changes: 69 additions & 2 deletions axi/axi4/rtl/AxiPkg.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -261,8 +261,29 @@ package AxiPkg is
totalBytes : slv;
address : slv)
return slv;

-- Caclulate the byte count for a read request

type AxiLenType is record
valid : slv(1 downto 0);
max : natural; -- valid(0)
req : natural; -- valid(0)
value : slv(7 downto 0);-- valid(1)
end record AxiLenType;
constant AXI_LEN_INIT_C : AxiLenType := (
valid => "00",
value => (others => '0'),
max => 0,
req => 0);
procedure getAxiLenProc (
-- Input
axiConfig : in AxiConfigType;
burstBytes : in integer range 1 to 4096 := 4096;
totalBytes : in slv;
address : in slv;
-- Pipelined signals
r : in AxiLenType;
v : inout AxiLenType);

-- Calculate the byte count for a read request
function getAxiReadBytes (
axiConfig : AxiConfigType;
axiRead : AxiReadMasterType)
Expand Down Expand Up @@ -369,6 +390,52 @@ package body AxiPkg is
return getAxiLen(axiConfig, min);

end function getAxiLen;

-- getAxiLenProc is functionally the same as getAxiLen()
-- but breaks apart the two comparator operations in getAxiLen()
-- into two separate clock cycles (instead of one), which helps
-- with meeting timing by breaking apart this long combinatorial chain
procedure getAxiLenProc (
-- Input
axiConfig : in AxiConfigType;
burstBytes : in integer range 1 to 4096 := 4096;
totalBytes : in slv;
address : in slv;
-- Pipelined signals
r : in AxiLenType;
v : inout AxiLenType) is
variable min : natural;
begin

--------------------
-- First Clock cycle
--------------------

-- Update valid flag for max/req
v.valid(0) := '1';

-- Check for 4kB boundary
v.max := 4096 - conv_integer(unsigned(address(11 downto 0)));

if (totalBytes < burstBytes) then
v.req := conv_integer(totalBytes);
else
v.req := burstBytes;
end if;

---------------------
-- Second Clock cycle
---------------------

-- Update valid flag for value
v.valid(1) := r.valid(0);

min := minimum(r.req, r.max);

-- Return the AXI Length value
v.value := getAxiLen(axiConfig, min);

end procedure;

-- Calculate the byte count for a read request
function getAxiReadBytes (
Expand Down
11 changes: 8 additions & 3 deletions axi/dma/rtl/AxiStreamDmaV2Read.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,7 @@ architecture rtl of AxiStreamDmaV2Read is
dmaRdDescRet : AxiReadDmaDescRetType;
first : sl;
leftovers : sl;
axiLen : AxiLenType;
rMaster : AxiReadMasterType;
sMaster : AxiStreamMasterType;
reqState : ReqStateType;
Expand All @@ -105,6 +106,7 @@ architecture rtl of AxiStreamDmaV2Read is
dmaRdDescRet => AXI_READ_DMA_DESC_RET_INIT_C,
first => '0',
leftovers => '0',
axiLen => AXI_LEN_INIT_C,
rMaster => axiReadMasterInit(AXI_CONFIG_G, "01", "0000"),
sMaster => axiStreamMasterInit(AXIS_CONFIG_G),
reqState => IDLE_S,
Expand Down Expand Up @@ -237,19 +239,22 @@ begin
end if;
----------------------------------------------------------------------
when ADDR_S =>
-- Determine transfer size aligned to 4k boundaries
getAxiLenProc(AXI_CONFIG_G, BURST_BYTES_G, r.reqSize, r.dmaRdDescReq.address,r.axiLen,v.axiLen);
-- Check if ready to make memory request
if (r.rMaster.arvalid = '0') then
if (r.rMaster.arvalid = '0') and (v.axiLen.valid = "11") then
-- Set the memory address
v.rMaster.araddr(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 0) := r.dmaRdDescReq.address(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 0);
-- Determine transfer size aligned to 4k boundaries
v.rMaster.arlen := getAxiLen(AXI_CONFIG_G, BURST_BYTES_G, r.reqSize, r.dmaRdDescReq.address);
-- Latch AXI arlen value
v.rMaster.arlen := v.axiLen.value;
-- Check for the following:
-- 1) There is enough room in the FIFO for a burst
-- 2) pending flag
-- 3) Last transaction already completed
if (pause = '0') and (r.pending = false) and (notReqDone = '1') then
-- Set the flag
v.rMaster.arvalid := '1';
v.axiLen.valid := "00";
-- Next state
v.state := MOVE_S;
v.reqState := NEXT_S;
Expand Down
12 changes: 8 additions & 4 deletions axi/dma/rtl/AxiStreamDmaV2Write.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,7 @@ architecture rtl of AxiStreamDmaV2Write is
ackCount : slv(31 downto 0);
stCount : slv(15 downto 0);
awlen : slv(AXI_CONFIG_G.LEN_BITS_C-1 downto 0);
axiLen : AxiLenType;
wMaster : AxiWriteMasterType;
slave : AxiStreamSlaveType;
state : StateType;
Expand All @@ -100,6 +101,7 @@ architecture rtl of AxiStreamDmaV2Write is
ackCount => (others => '0'),
stCount => (others => '0'),
awlen => (others => '0'),
axiLen => AXI_LEN_INIT_C,
wMaster => axiWriteMasterInit(AXI_CONFIG_G, '1', "01", "0000"),
slave => AXI_STREAM_SLAVE_INIT_C,
state => RESET_S,
Expand Down Expand Up @@ -263,19 +265,21 @@ begin
v.stCount := (others=>'0');
v.continue := '0';
v.lastUser := (others=>'0');
-- Determine transfer size aligned to 4k boundaries
getAxiLenProc(AXI_CONFIG_G,BURST_BYTES_G,r.dmaWrTrack.maxSize,r.dmaWrTrack.address,r.axiLen,v.axiLen);
-- Address can be sent
if (v.wMaster.awvalid = '0') then
if (v.wMaster.awvalid = '0') and (v.axiLen.valid = "11") then
-- Set the memory address
v.wMaster.awaddr(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 0) :=
r.dmaWrTrack.address(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 0);
-- Determine transfer size aligned to 4k boundaries
v.wMaster.awlen := getAxiLen(AXI_CONFIG_G,BURST_BYTES_G,r.dmaWrTrack.maxSize,r.dmaWrTrack.address);
-- Latch AXI awlen value
v.awlen := v.wMaster.awlen(AXI_CONFIG_G.LEN_BITS_C-1 downto 0);
v.wMaster.awlen := v.axiLen.value;
v.awlen := v.axiLen.value(AXI_CONFIG_G.LEN_BITS_C-1 downto 0);
-- Check if enough room
if pause = '0' then
-- Set the flag
v.wMaster.awvalid := '1';
v.axiLen.valid := "00";
-- Increment the counter
v.reqCount := r.reqCount + 1;
-- Next state
Expand Down
4 changes: 2 additions & 2 deletions ethernet/TenGigEthCore/gtx7/ip/TenGigEthGtx7Core.dcp
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Git LFS file not shown
13 changes: 7 additions & 6 deletions ethernet/TenGigEthCore/gtx7/ip/TenGigEthGtx7Core.xci
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClkRate">156.25</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Timer_Format">Time_of_day</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverInExample">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.autonegotiation">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.base_kr">BASE-R</spirit:configurableElementValue>
Expand All @@ -47,27 +47,28 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg676</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DClkRate" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TransceiverControl" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
Expand Down
81 changes: 65 additions & 16 deletions ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
-- File : TenGigEthGtx7.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2015-02-12
-- Last update: 2018-01-08
-- Last update: 2018-07-30
-------------------------------------------------------------------------------
-- Description: 10GBASE-R Ethernet for Gtx7
-------------------------------------------------------------------------------
Expand All @@ -26,11 +26,11 @@ use work.EthMacPkg.all;

entity TenGigEthGtx7 is
generic (
TPD_G : time := 1 ns;
TPD_G : time := 1 ns;
-- AXI-Lite Configurations
EN_AXI_REG_G : boolean := false;
EN_AXI_REG_G : boolean := false;
-- AXI Streaming Configurations
AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C);
AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C);
port (
-- Local Configurations
localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C;
Expand All @@ -53,10 +53,16 @@ entity TenGigEthGtx7 is
txFault : in sl := '0';
txDisable : out sl;
-- Misc. Signals
extRst : in sl;
extRst : in sl := '0';
phyClk : in sl;
phyRst : in sl;
phyReady : out sl;
-- Transceiver Debug Interface
gtTxPreCursor : in slv(4 downto 0) := "00000";
gtTxPostCursor : in slv(4 downto 0) := "00000";
gtTxDiffCtrl : in slv(3 downto 0) := "1110";
gtRxPolarity : in sl := '0';
gtTxPolarity : in sl := '0';
-- Quad PLL Ports
qplllock : in sl;
qplloutclk : in sl;
Expand All @@ -66,7 +72,7 @@ entity TenGigEthGtx7 is
gtTxP : out sl;
gtTxN : out sl;
gtRxP : in sl;
gtRxN : in sl);
gtRxN : in sl);
end TenGigEthGtx7;

architecture mapping of TenGigEthGtx7 is
Expand Down Expand Up @@ -119,7 +125,28 @@ architecture mapping of TenGigEthGtx7 is
drp_drdy_i : in std_logic;
drp_drpdo_i : in std_logic_vector(15 downto 0);
tx_disable : out std_logic;
pma_pmd_type : in std_logic_vector(2 downto 0));
pma_pmd_type : in std_logic_vector(2 downto 0);
gt0_eyescanreset : in std_logic;
gt0_eyescandataerror : out std_logic;
gt0_txbufstatus : out std_logic_vector(1 downto 0);
gt0_rxbufstatus : out std_logic_vector(2 downto 0);
gt0_eyescantrigger : in std_logic;
gt0_rxcdrhold : in std_logic;
gt0_txprbsforceerr : in std_logic;
gt0_txpolarity : in std_logic;
gt0_rxpolarity : in std_logic;
gt0_rxprbserr : out std_logic;
gt0_txpmareset : in std_logic;
gt0_rxpmareset : in std_logic;
gt0_txresetdone : out std_logic;
gt0_rxresetdone : out std_logic;
gt0_rxdfelpmreset : in std_logic;
gt0_rxlpmen : in std_logic;
gt0_dmonitorout : out std_logic_vector(7 downto 0);
gt0_rxrate : in std_logic_vector(2 downto 0);
gt0_txprecursor : in std_logic_vector(4 downto 0);
gt0_txpostcursor : in std_logic_vector(4 downto 0);
gt0_txdiffctrl : in std_logic_vector(3 downto 0));
end component;

signal mAxiReadMaster : AxiLiteReadMasterType;
Expand Down Expand Up @@ -155,7 +182,7 @@ architecture mapping of TenGigEthGtx7 is
signal macRxAxisCtrl : AxiStreamCtrlType;
signal macTxAxisMaster : AxiStreamMasterType;
signal macTxAxisSlave : AxiStreamSlaveType;

begin

phyReady <= status.phyReady;
Expand All @@ -182,7 +209,7 @@ begin
mAxiReadMaster => mAxiReadMaster,
mAxiReadSlave => mAxiReadSlave,
mAxiWriteMaster => mAxiWriteMaster,
mAxiWriteSlave => mAxiWriteSlave);
mAxiWriteSlave => mAxiWriteSlave);

txDisable <= status.txDisable;

Expand All @@ -199,7 +226,7 @@ begin
-- Output
dataOut(0) => status.sigDet,
dataOut(1) => status.txFault,
dataOut(2) => status.txUsrRdy);
dataOut(2) => status.txUsrRdy);

--------------------
-- Ethernet MAC core
Expand Down Expand Up @@ -227,7 +254,7 @@ begin
xgmiiRxd => phyRxd,
xgmiiRxc => phyRxc,
xgmiiTxd => phyTxd,
xgmiiTxc => phyTxc);
xgmiiTxc => phyTxc);

-----------------
-- 10GBASE-R core
Expand Down Expand Up @@ -288,7 +315,29 @@ begin
drp_daddr_i => drpAddr,
drp_di_i => drpDi,
drp_drdy_i => drpRdy,
drp_drpdo_i => drpDo);
drp_drpdo_i => drpDo,
-- Transceiver Debug Interface
gt0_eyescanreset => '0',
gt0_eyescandataerror => open,
gt0_txbufstatus => open,
gt0_rxbufstatus => open,
gt0_eyescantrigger => '0',
gt0_rxcdrhold => '0',
gt0_txprbsforceerr => '0',
gt0_txpolarity => gtTxPolarity,
gt0_rxpolarity => gtRxPolarity,
gt0_rxprbserr => open,
gt0_txpmareset => '0',
gt0_rxpmareset => '0',
gt0_txresetdone => open,
gt0_rxresetdone => open,
gt0_rxdfelpmreset => '0',
gt0_rxlpmen => '0',
gt0_dmonitorout => open,
gt0_rxrate => (others => '0'),
gt0_txprecursor => gtTxPreCursor,
gt0_txpostcursor => gtTxPostCursor,
gt0_txdiffctrl => gtTxDiffCtrl);

-------------------------------------
-- 10GBASE-R's Reset Module
Expand All @@ -310,7 +359,7 @@ begin
rstCntDone => status.rstCntDone,
-- Quad PLL Ports
qplllock => status.qplllock,
qpllRst => qpllRst);
qpllRst => qpllRst);

-------------------------------
-- Configuration Vector Mapping
Expand All @@ -331,8 +380,8 @@ begin
--------------------------------
U_TenGigEthReg : entity work.TenGigEthReg
generic map (
TPD_G => TPD_G,
EN_AXI_REG_G => EN_AXI_REG_G)
TPD_G => TPD_G,
EN_AXI_REG_G => EN_AXI_REG_G)
port map (
-- Local Configurations
localMac => localMac,
Expand All @@ -346,6 +395,6 @@ begin
axiWriteSlave => mAxiWriteSlave,
-- Configuration and Status Interface
config => config,
status => status);
status => status);

end mapping;
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