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@ruck314 ruck314 released this 22 Jun 00:13
· 3829 commits to main since this release
v1.8.5
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Pull Requests

  1. #241 - v1.8.5 release candidate
  2. #239 - PGPv3 Updates
  3. #237 - PGPv3: GTX7 Update
  4. #232 - Including local busy into RSSI's header
  5. #242 - adding zynquplus support to surf
  6. #221 - New UART Features
  7. #238 - SsiPrbsRx Update
  8. #235 - Seperate cache settings in Axis gen2 DMA
  9. #233 - Fix natural range spec outside of max bounds
  10. #236 - GTX7's QPLL Bug Fix
  11. #234 - Add xvcSrv to .gitignore

Pull Request Details

v1.8.5 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Jun 21 16:55:08 2018 -0700
Pull: #241 (2275 additions, 456 deletions, 55 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Fixed flow control bug in AxiStreamPacketizer2.vhd
  • Fixed overflow synchronization issue
  • Updated python to match FW error counter size
  • Added pause/overflow event message sending to PGPv3 TX protocol
  • Added SOF check to SsiPrbsRx
  • Updated AXIS flow control procedure to SsiPrbsRx
  • Added 3.125Gbps support to PGPv3 GTX7
  • GTX7's QPLL Bug Fix
  • Seperate cache settings in Axis gen2 DMA
  • Add xvcSrv to .gitignore
  • Including local busy into RSSI's header
  • UART Updates (#221)
  • Added zynquplus support

PGPv3 Updates
Author: Larry Ruckman [email protected]
Date: Thu Jun 14 08:45:08 2018 -0700
Pull: #239 (1789 additions, 127 deletions, 26 files changed)
Branch: slaclab/pgp3-overflow

Notes:

Description

  • Fixed flow control bug in AxiStreamPacketizer2.vhd
  • Fixed overflow synchronization issue
  • Updated python to match FW error counter size
  • Added pause/overflow event message sending to PGPv3 TX protocol

PGPv3: GTX7 Update
Author: Larry Ruckman [email protected]
Date: Tue Jun 12 14:32:35 2018 -0700
Pull: #237 (1616 additions, 34 deletions, 12 files changed)
Branch: slaclab/PGPv3-gtx7-update

Notes:

Description

Adding 3.125Gbps support to PGPv3 GTX7

Including local busy into RSSI's header
Author: Larry Ruckman [email protected]
Date: Tue May 22 14:36:31 2018 -0700
Pull: #232 (176 additions, 82 deletions, 10 files changed)
Branch: slaclab/rssi-busy

Notes:

Description

Including local busy into RSSI's header

adding zynquplus support to surf
Author: Larry Ruckman [email protected]
Date: Mon Jun 18 13:37:09 2018 -0700
Pull: #242 (90 additions, 99 deletions, 8 files changed)
Branch: slaclab/zynquplus

Notes:

Description

Adding zynquplus support to surf

New UART Features
Author: Larry Ruckman [email protected]
Date: Thu Jun 14 12:36:55 2018 -0700
Pull: #221 (117 additions, 48 deletions, 4 files changed)
Branch: slaclab/uart-dev

Notes:

Description

Added generic for enabling the parity bit.

  • PARITY_EN_G : integer range 0 to 1 := 0;

Added generic for selecting parity.

  • PARITY_G : string := "NONE";
  • Options are: "NONE", "EVEN", "ODD"

Added generic for selecting data-width of 5, 6, 7, or 8.

  • DATA_WIDTH_G : integer range 5 to 8 := 8;

Added extra state (PARITY_S) in UartRX.vhd for parity checking.

SsiPrbsRx Update
Author: Larry Ruckman [email protected]
Date: Wed Jun 13 11:45:00 2018 -0700
Pull: #238 (65 additions, 73 deletions, 1 files changed)
Branch: slaclab/SsiPrbsRx

Notes:

Description

  1. Added SOF check
  2. Updated AXIS flow control procedure

JIRA

ESCORE-355

Seperate cache settings in Axis gen2 DMA
Author: Larry Ruckman [email protected]
Date: Thu May 31 15:41:07 2018 -0700
Pull: #235 (26 additions, 16 deletions, 3 files changed)
Branch: slaclab/ESCORE-354
Jira: https://jira.slac.stanford.edu/issues/ESCORE-354

Notes:

This PR will add a separate buffer cache settings for the AXIS gen2 DMA engine. This is required because the proper value for the rd cache bits is different than the write setting.

Fix natural range spec outside of max bounds
Author: Benjamin Reese [email protected]
Date: Tue May 22 14:34:32 2018 -0700
Pull: #233 (10 additions, 10 deletions, 1 files changed)
Branch: slaclab/WatchDogRst-fix

Notes:

Description

Range specified for DURATION_G was greater than max 'natural'.
Removed the range spec since it was redundant anyway.

GTX7's QPLL Bug Fix
Author: Larry Ruckman [email protected]
Date: Fri Jun 8 11:22:35 2018 -0700
Pull: #236 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/gtx7-update

Notes:

Description

Based on UG476 (v1.12), setting BGRCALOVRD to 5'b11111
"Reserved. This port must be set to 5'b11111. This value should not be modified."

Add xvcSrv to .gitignore
Author: Benjamin Reese [email protected]
Date: Wed May 23 13:01:36 2018 -0700
Pull: #234 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/xvcSrv-ignore

Notes:

Description

Compiled xvcSrv binary causes dirty build flag if not ignored by git.

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