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Minor Release v2.40.0
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@ruck314 ruck314 released this 03 Apr 18:14
· 602 commits to main since this release
v2.40.0
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Pull Requests Since v2.39.0

Unlabeled

  1. #1056 - bug fix for AxiLitePkg.vhd to make AxiLiteWrite work for Cadence Genus
  2. #1057 - Sugoi Post-Synthesis Simulation Reset Support

Pull Request Details

bug fix for AxiLitePkg.vhd to make AxiLiteWrite work for Cadence Genus
Author: Larry Ruckman [email protected]
Date: Mon Apr 3 11:08:44 2023 -0700
Pull: #1056 (96 additions, 8 deletions, 1 files changed)
Branch: slaclab/axi-lite-genus-dev

Notes:

Description

  • With the default of constVal = "X", Cadence Genus quietly fails to synthesis the if (constVal /= "X") then statement and optimizes the write data bus away away in synthesis
  • This proposed solution is just add more function overloading for the constVal argument is not used

Sugoi Post-Synthesis Simulation Reset Support
Author: Larry Ruckman [email protected]
Date: Fri Mar 31 10:44:42 2023 -0700
Pull: #1057 (44 additions, 24 deletions, 5 files changed)
Branch: slaclab/sugoi-RST_ASYNC_G

Notes:

Description

  • adding RST_ASYNC_G support to these modules so we can do a ASYNC reset at power up after ASIC post-synthsis.
  • This removes the 'X' signals such that '+vcs+initreg+0' is nolonger required
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