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@ruck314 ruck314 released this 18 May 18:05
· 2096 commits to main since this release
v2.5.0
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Pull Requests Since v2.4.0

Bug

  1. #661 - SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd

Unlabeled

  1. #669 - Release Candidate v2.5.0
  2. #663 - Add AXIL-DRP interface for GigE GTX7
  3. #665 - Adding AxiStreamResizeTb.vhd
  4. #662 - Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd
  5. #666 - Resolving double YAML load issue
  6. #664 - Add register verify for the read/write registers
  7. #667 - Update _Lmk04828.py
  8. #668 - Cache ClinkSerialRx response for reading

Pull Request Details

SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd
Author: Larry Ruckman [email protected]
Date: Thu Apr 30 16:03:38 2020 -0700
Pull: #661 (471 additions, 27 deletions, 4 files changed)
Branch: slaclab/SrpV3AxiTb
Labels: bug

Notes:

Description

  • Added SrpV3AxiTb.vhd
  • AXI stream resize bug fix for SrpV3Core.vhd
    • bug fix for when external AXIS is not 32-bit wide tData

Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd
Author: Larry Ruckman [email protected]
Date: Thu May 14 09:03:31 2020 -0700
Pull: #662 (71 additions, 31 deletions, 2 files changed)
Branch: slaclab/boxcarPipeline

Notes:

trying to address timing closure for MPS Central node. Modified BoxCarIntegrator to add register output to memory used and pipeline for processing. It is optional controlled by generic options. It is not tested yet.

Add AXIL-DRP interface for GigE GTX7
Author: Benjamin Reese [email protected]
Date: Fri May 15 22:35:15 2020 -0700
Pull: #663 (1819 additions, 78 deletions, 7 files changed)
Branch: slaclab/gtx7-drp

Notes:

Description

The GigEth GTX7 DCP core was regenerated in slaclab/surf-dcp-targets#2 to add DRP and txdiffctrl ports. This DCP has been copied into SURF. The DRP ports have been attached to an AxiLiteToDrp bridge and the TX drive strength ports brought out to top level ports.

Some minor cleanup was also done on the GigEthReg python Device class.

Details

Add register verify for the read/write registers
Author: Larry Ruckman [email protected]
Date: Wed May 13 08:53:25 2020 -0700
Pull: #664 (15 additions, 1 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-652
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-652

Notes:

Description

  • Add register verify for the read/write registers to catch broken SPI interfaces

Adding AxiStreamResizeTb.vhd
Author: Larry Ruckman [email protected]
Date: Thu May 14 09:03:08 2020 -0700
Pull: #665 (292 additions, 0 deletions, 1 files changed)
Branch: slaclab/ESCORE-560
Jira: https://jira.slac.stanford.edu/issues/ESCORE-560

Notes:

Resolving double YAML load issue
Author: Larry Ruckman [email protected]
Date: Thu May 14 13:40:59 2020 -0700
Pull: #666 (60 additions, 8 deletions, 4 files changed)
Branch: slaclab/ESCRYODET-567
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-567

Notes:

Description

  • Update Init() delays in Adc32Rf45, Dac38J84 and Lmk04828

Update _Lmk04828.py
Author: Larry Ruckman [email protected]
Date: Thu May 14 20:31:36 2020 -0700
Pull: #667 (3 additions, 3 deletions, 2 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Bug fix

Cache ClinkSerialRx response for reading
Author: Larry Ruckman [email protected]
Date: Fri May 15 19:45:12 2020 -0700
Pull: #668 (3 additions, 1 deletions, 1 files changed)
Branch: slaclab/clink_serial_read
Issues: #668

Notes:

Description

Modify _ClinkSerialRx.py to cache received response on serial link to allow read result to be retrieved.

Release Candidate v2.5.0
Author: Larry Ruckman [email protected]
Date: Mon May 18 11:02:45 2020 -0700
Pull: #669 (2734 additions, 149 deletions, 21 files changed)
Branch: slaclab/pre-release
Issues: #664, #665, #662, #666, #667, #668, #663, #661

Notes:

Description

  • Add register verify for the read/write registers #664
  • Adding AxiStreamResizeTb.vhd #665
  • Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd #662
  • Resolving double YAML load issue #666
  • Update _Lmk04828.py #667
  • Cache ClinkSerialRx response for reading #668
  • Add AXIL-DRP interface for GigE GTX7 #663
  • SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd #661
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