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@ruck314 ruck314 released this 17 Jul 00:00
· 1934 commits to main since this release
v2.7.0
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Pull Requests Since v2.6.7

Enhancement

  1. #707 - Allow per destination buffer limits in DMA engine

Unlabeled

  1. #708 - Release Candidate v2.7.0
  2. #711 - Adding SlvDelayRam.vhd
  3. #710 - AxiStreamDmaV2Desc.vhd Updates
  4. #713 - Bug fixes for UartTx.vhd & ClinkUart.vhd
  5. #712 - Fix AXI-Lite protocol error in AxiLiteCrossbar
  6. #715 - Removing Accidental Commit of Python Debugger By User
  7. #717 - Fixed typo in ClinkChannel.py
  8. #709 - Update _EM22xx.py

Pull Request Details

Allow per destination buffer limits in DMA engine
Author: Larry Ruckman [email protected]
Date: Thu Jul 9 17:27:59 2020 -0700
Pull: #707 (147 additions, 26 deletions, 6 files changed)
Branch: slaclab/dest_buffer_limits
Labels: enhancement

Notes:

The goal of this PR is to allow a limit on the number of outstanding DMA buffers any single destination can be using. This will allow the client to set a max buffer count after opening a channel on the driver. The end result is a flow control signal which extends outside of the dma engine to the mux point for a set of streams.

In order to accomplish this we need to communicate this per dest pause to the mux stage. Here I propose adding a destPause vector to the AxiStreamCtrl record and using this record in the AxiStreamMux device.

Release Candidate v2.7.0
Author: Larry Ruckman [email protected]
Date: Thu Jul 16 16:30:55 2020 -0700
Pull: #708 (546 additions, 72 deletions, 14 files changed)
Branch: slaclab/pre-release
Issues: #707, #710, #711, #712, #713, #709, #715, #717

Notes:

New Features

  • Allow per destination buffer limits in DMA engine #707
    • AxiStreamDmaV2Desc.vhd Updates #710
  • Adding SlvDelayRam.vhd #711

Bug Fixes

  • Fix AXI-Lite protocol error in AxiLiteCrossbar #712
  • Bug fixes for UartTx.vhd & ClinkUart.vhd #713
  • Bug fixes for _EM22xx.py #709
  • Removing Accidental Commit of Python Debugger By User #715
  • Fixed typo in ClinkChannel.py #717

Update _EM22xx.py
Author: Larry Ruckman [email protected]
Date: Fri Jul 10 16:05:47 2020 -0700
Pull: #709 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/EM22xx-patch

Notes:

Description

  • Fixed the DUTY_CYCLE units
    • From kHz to %

AxiStreamDmaV2Desc.vhd Updates
Author: Larry Ruckman [email protected]
Date: Fri Jul 10 16:09:43 2020 -0700
Pull: #710 (74 additions, 43 deletions, 1 files changed)
Branch: slaclab/DmaV2-dev

Notes:

Description

  • implementing intHoldoff and idBuff with DSP primatives
    • Helps with making timing
  • reset idBuffCount if DMA disabled
    • Plus some code clean up on resetting counters/indexs when DMA disabled
  • bug fixes for intHoldoffCount=intHoldoff and idBuffCount=idBuffThold
    • Specifically fixes the issue where BG[X].Count = BG[X].Threshold + 1 when asserting pause
  • Removing roll over or roll underconditions in idBuffCount
    • should NEVER happen and don't want to mask out or hide a potential problem

Adding SlvDelayRam.vhd
Author: Larry Ruckman [email protected]
Date: Tue Jul 14 13:51:51 2020 -0700
Pull: #711 (309 additions, 0 deletions, 2 files changed)
Branch: slaclab/SlvDelayRam
Issues: #714

Notes:

Description

  • Similar to SlvDelay.vhd but with support for inferring LUTRAM, BRAM or URAM

Fix AXI-Lite protocol error in AxiLiteCrossbar
Author: Larry Ruckman [email protected]
Date: Thu Jul 16 12:25:07 2020 -0700
Pull: #712 (16 additions, 10 deletions, 1 files changed)
Branch: slaclab/axil-xbar-fix
Issues: #706

Notes:

Description

The AXI-Lite spec requires that the address cycle complete before the data cycle is initiated. The AxiLiteCrossbar was violating this rule on its slave side for both reads and writes, but only in the case of decode errors. In that case, the data response was being sent concurrent with the address acknowledge. This is now fixed.

Related

This is a fix for #706

Bug fixes for UartTx.vhd & ClinkUart.vhd
Author: Larry Ruckman [email protected]
Date: Mon Jul 13 17:39:20 2020 -0700
Pull: #713 (19 additions, 8 deletions, 2 files changed)
Branch: slaclab/clink-uart-patch

Notes:

Description

  • bug fix for UartTx.vhd baud rate
  • bug fix for ClinkUart baud rate generation

Removing Accidental Commit of Python Debugger By User
Author: Larry Ruckman [email protected]
Date: Wed Jul 15 15:31:23 2020 -0700
Pull: #715 (0 additions, 4 deletions, 1 files changed)
Branch: slaclab/ClinkSerialTx-pdb-removal

Notes:

Description

  • ClinkSerialTx is the general class and should be sub-class if the user wants to add custom debugger break point with strings that start with '@sn?'

Fixed typo in ClinkChannel.py
Author: Larry Ruckman [email protected]
Date: Wed Jul 15 15:31:13 2020 -0700
Pull: #717 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/FrameMode-description

Notes:

Description

  • Fixed typo in the FrameMode's description
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