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@ruck314 ruck314 released this 01 Sep 16:52
· 1823 commits to main since this release
v2.9.0
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Pull Requests Since v2.8.1

Bug

  1. #741 - Bug fix for AxiStreamDmaRead.vhd and AxiStreamDmaWrite.vhd

Enhancement

  1. #746 - Ip integrator Support
  2. #739 - adding AxiMonAxiL and AxiRateGen
  3. #745 - adding AxiStreamGearbox.vhd
  4. #742 - Adding TPD_G support to XPM RAMs
  5. #744 - JesdTx Update

Unlabeled

  1. #740 - Release Candidate v2.9.0
  2. #743 - Update Dac38J84 CPSW YAML definition
  3. #732 - Bring out SYNTH_MODE_G generic for internal RAMs

Pull Request Details

Bring out SYNTH_MODE_G generic for internal RAMs
Author: Larry Ruckman [email protected]
Date: Mon Aug 31 15:56:28 2020 -0700
Pull: #732 (178 additions, 128 deletions, 18 files changed)
Branch: slaclab/synth_mode_g

Notes:

Description

This PR exposes the SYNTH_MOD_G generic from internal RAMs in modules where it makes sense to have this configurable.

Details

For Xilinx builds, the SYNTH_MOD_G => "xpm" option seems to provide much better timing closure for very large RAMs compared to "inferred". It is useful to therefore to make the option available when possible.

adding AxiMonAxiL and AxiRateGen
Author: Larry Ruckman [email protected]
Date: Fri Aug 14 16:22:33 2020 -0700
Pull: #739 (751 additions, 63 deletions, 10 files changed)
Branch: slaclab/axi4-monitor
Labels: enhancement

Notes:

Description

  • Re-propose the existing AXI stream monitor as a AXI4 memory monitor
  • Adding AxiRateGen, which support programmable read/write burst rate and frame size

Release Candidate v2.9.0
Author: Larry Ruckman [email protected]
Date: Tue Sep 1 09:48:25 2020 -0700
Pull: #740 (3324 additions, 422 deletions, 52 files changed)
Branch: slaclab/pre-release
Issues: #739, #741, #742, #743, #744, #745, #746, #732
Labels: release

Notes:

Description

  • adding AxiMonAxiL and AxiRateGen #739
  • Bug fix for AxiStreamDmaRead.vhd and AxiStreamDmaWrite.vhd #741
  • Adding TPD_G support to XPM RAMs #742
  • Update Dac38J84 CPSW YAML definition #743
  • JesdTx Update #744
  • adding AxiStreamGearbox.vhd #745
  • Ip integrator Support #746
  • Bring out SYNTH_MODE_G generic for internal RAMs #732

Bug fix for AxiStreamDmaRead.vhd and AxiStreamDmaWrite.vhd
Author: Larry Ruckman [email protected]
Date: Mon Aug 17 08:20:15 2020 -0700
Pull: #741 (6 additions, 2 deletions, 2 files changed)
Branch: slaclab/dma-v1-bug-fix
Labels: bug

Notes:

Description

  • bug fix for super wide AXI4 memory bus (> 128-bits) and bypassing AxiStreamShift.vhd

Adding TPD_G support to XPM RAMs
Author: Larry Ruckman [email protected]
Date: Fri Aug 21 13:25:45 2020 -0700
Pull: #742 (13 additions, 5 deletions, 2 files changed)
Branch: slaclab/xpm-ram-TPD_G
Labels: enhancement

Notes:

Description

  • similar to the XPM FIFOs, adding TPD_G output delay to XPM RAMs
  • TPD_G makes viewing the simulation behavior a lot easier

Update Dac38J84 CPSW YAML definition
Author: Larry Ruckman [email protected]
Date: Thu Aug 20 14:57:32 2020 -0700
Pull: #743 (249 additions, 222 deletions, 1 files changed)
Branch: slaclab/ESLCOMMON-245
Jira: https://jira.slac.stanford.edu/issues/ESLCOMMON-245

Notes:

Update the Dac38J84 YAML definition, based on the definition used by Rogue's device.

Description

The Dac38J84 YAML definition is not up to date with the latest changes done in the Rogue version. So, this PR updates this definition. It mainly:

  • Add the missing JesdRstN register,
  • Adds the NcoSync command,
  • Adds a missing register in the ClearAlarms command, and
  • Breaks down the ID register into VersionId and VendorId.

It also change the formatting for better readability.

JIRA

https://jira.slac.stanford.edu/browse/LIMRLLRF-17

JesdTx Update
Author: Larry Ruckman [email protected]
Date: Thu Aug 27 08:54:07 2020 -0700
Pull: #744 (6 additions, 2 deletions, 2 files changed)
Branch: slaclab/ESCRYODET-710
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-710
Labels: enhancement

Notes:

Description

  • adding dacReady_o to JESD TX

adding AxiStreamGearbox.vhd
Author: Larry Ruckman [email protected]
Date: Thu Aug 27 09:23:09 2020 -0700
Pull: #745 (371 additions, 0 deletions, 1 files changed)
Branch: slaclab/axis-gearbox
Labels: enhancement

Notes:

Description

  • This module is based on AxiStreamResize.vhd and Gearbox.vhd
  • Unlike AxiStreamResize.vhd which only supports resizing of word multiple, AxiStreamGearbox.vhd can resize any byte width to any byte width
    • tDests interleaving still not supported
  • I have benchmarked the resources to the Xilinx IP core for resizing and AxiStreamGearbox.vhd uses about half as many LUTs as the IP core.

Ip integrator Support
Author: Larry Ruckman [email protected]
Date: Fri Aug 28 09:15:37 2020 -0700
Pull: #746 (1750 additions, 0 deletions, 16 files changed)
Branch: slaclab/ip_integrator-update
Labels: enhancement

Notes:

Description

  • Adding Ip integrator Support
    • axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd
    • axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd
    • axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd
    • AxiDualPortRamIpIntegrator.vhd: Wrapper on AxiDualPortRam
    • axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd
    • axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd
    • axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd
    • axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd
    • axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd
    • base/general/ip_integrator/MasterRamIpIntegrator.vhd
    • base/general/ip_integrator/SlaveRamIpIntegrator.vhd
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