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Merge pull request #69 from sledgeh4w/split-out-instruction-and-fixup
Split out instruction and fixup modules
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Original file line number | Diff line number | Diff line change |
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import re | ||
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from unicorn.unicorn import arm64_const | ||
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class AutomicInstruction: | ||
"""Execute an atomic instruction (ldxr, ldadd, ldset, swp, cas). | ||
The iOS system libraries will use some atomic instructions from ARM v8.1. | ||
However, Unicorn doesn't support these instructions, so we need to simulation | ||
them ourselves. | ||
""" | ||
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supports = ("ldxr", "ldadd", "ldset", "swp", "cas") | ||
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def __init__(self, emu, code: bytes): | ||
self.emu = emu | ||
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self._inst = next(self.emu.cs.disasm_lite(code, 0)) | ||
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if not any((self._inst[2].startswith(t) for t in self.supports)): | ||
raise ValueError("Unsupported instruction: %s" % self._inst[0]) | ||
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match = re.match(r"(\w+), \[(\w+)]", self._inst[3]) | ||
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if not match: | ||
match = re.match(r"(\w+), (\w+), \[(\w+)]", self._inst[3]) | ||
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if not match: | ||
raise ValueError("Invalid instruction: %s" % self._inst[3]) | ||
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# Parse operation registers | ||
self._regs = [] | ||
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for reg in match.groups(): | ||
attr = f"UC_ARM64_REG_{reg.upper()}" | ||
self._regs.append(getattr(arm64_const, attr)) | ||
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# Parse operation bits | ||
if self._inst[2].endswith("b"): | ||
self._op_bits = 8 | ||
elif re.search(r"w(\d+)", self._inst[3]): | ||
self._op_bits = 32 | ||
else: | ||
self._op_bits = 64 | ||
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def execute(self): | ||
address = self.emu.uc.reg_read(self._regs[-1]) | ||
value = self.emu.read_int(address, self._op_bits // 8) | ||
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result = None | ||
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if self._inst[2].startswith("ldxr"): | ||
self.emu.uc.reg_write(self._regs[0], value) | ||
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elif self._inst[2].startswith("ldadd"): | ||
self.emu.uc.reg_write(self._regs[1], value) | ||
result = value + self.emu.uc.reg_read(self._regs[0]) | ||
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elif self._inst[2].startswith("ldset"): | ||
self.emu.uc.reg_write(self._regs[1], value) | ||
result = value | self.emu.uc.reg_read(self._regs[0]) | ||
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elif self._inst[2].startswith("swp"): | ||
self.emu.uc.reg_write(self._regs[1], value) | ||
result = self.emu.uc.reg_read(self._regs[0]) | ||
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elif self._inst[2].startswith("cas"): | ||
n = self.emu.uc.reg_read(self._regs[0]) | ||
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self.emu.uc.reg_write(self._regs[0], value) | ||
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if n == value: | ||
result = self.emu.uc.reg_read(self._regs[1]) | ||
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if result is not None: | ||
result %= 2**self._op_bits | ||
self.emu.write_int(address, result, self._op_bits // 8) |
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