Smartbench is a project with the objective of providing low cost, open source and open hardware implementations of instruments for electronic. The main target of this project are students of and hobbyist of electronics that can't afford (or don't want to) professional equipment, but would like to own the basic instruments.
(05/03/2018) Today, there is a prototipe of what we call the "mainboard". The mainboard is a digital oscilloscope based on an FPGA, with an available connector for future expansions. The main features of the oscilloscope are:
- Two channels with 20MSPS each
- 5MHz cut-off frequency of the analog front-end
- Input Voltage between -25V and 25V
- DC / AC coupling
- Trigger modes: normal, auto, single shot
- Voltage scales: 10 mV/div to 5 V/div, with sequence 1,2,5,10,...
- Timebase: {100 nsec/div to 1 sec/div, with sequence 1,2,5,10,...
The mainboard sources are split in three parts:
- Hardware (KiCad PCB Schematic, fab. files)
- FPGA Firmware (Verilog)
- Software (Python)
The HDL loaded to the FPGA. The HDL used is Verilog, and the FPGA is a Lattice iCE40HX4K. The work flow consists on synthesis, place and route, and program the FPGA. The tools for that are open source, credits to Clifford.
The tools used for synthetize, place and route and load to the FPGA are well described in http://www.clifford.at/icestorm/
- Yosys (Synthesis)
- Arachne-pnr (Place and Route)
- iCEstorm tools (Programming, time analysis, etc)
- Icarus Verilog (Verilog simulator)
- Cocotb (Python testbenchs)
- GTKwave (Waveforms visualization)
There is a folder for each module, containing the test files.
/hdl/modules/<module>/test_<name>/
Tests are executed by running Make in that folder.
The debug results are printed in the command prompt, and the waveform stored in the file waveform.vcd.
To visualize the waveform, open that file with GTKwave.