Timing path fix in vna_scanner

gateware/rtl/nco/mix2.v

@@ -41,6 +41,7 @@ logic                 state = 1'b0;
 
 nco2 #(.CALCTYPE(CALCTYPE)) nco2_i (
   .state(state),
+  .clk(clk),
   .clk_2x(clk_2x),
   .rst(rst),
   .phi0(phi0),
@@ -61,7 +62,7 @@ always @(posedge clk_2x) begin
   scos_q <= cos[18] ? scos[18:1] : cos[18:1];
 end
 
-always @(posedge clk_2x) begin
+always @(posedge clk) begin
   adci <= adc;
   adcq <= adc;
 end

gateware/rtl/nco/nco2.v

@@ -4,6 +4,7 @@
 module nco2 (
   state,
   clk_2x,
+  clk,
   rst,
   phi0,
   phi1,
@@ -13,6 +14,7 @@ module nco2 (
 
 input             state;
 input             clk_2x;
+input             clk;
 input             rst;
 input     [31:0]  phi0;
 input     [31:0]  phi1;
@@ -22,23 +24,23 @@ output    [18:0]  cos;
 logic [31:0]      angle0 = 32'h00;
 logic [31:0]      angle1 = 32'h00;
 
-logic phi0iszero = 1'b0;
-logic phi1iszero = 1'b0;
+//logic phi0iszero = 1'b0;
+//logic phi1iszero = 1'b0;
 
 parameter         CALCTYPE = 0;
 
-always @(posedge clk_2x) begin
-  phi0iszero <= ~(|phi0);
-  phi1iszero <= ~(|phi1);
-end
+//always @(posedge clk) begin
+//  phi0iszero <= ~(|phi0);
+//  phi1iszero <= ~(|phi1);
+//end
 
 always @(posedge clk_2x) begin
   if (state) begin
     angle1 <= angle0 + phi1;
-    angle0 <= (phi0iszero) ? 32'h00 : angle1;
+    angle0 <= rst ? 32'h00 : angle1;
   end else begin
     angle1 <= angle0 + phi0;
-    angle0 <= (phi1iszero) ? 32'h00 : angle1;
+    angle0 <= rst ? 32'h00 : angle1;
   end
 end
 

gateware/rtl/radio_openhpsdr1/radio.v

@@ -346,6 +346,7 @@ always @ (rx_rate) begin
 end
 
 logic [31:0]  tx0_phase;    // For VNAscan, starts at tx_phase0 and increments for vna_count points; else tx_phase0.
+logic [ 1:0]  tx0_phase_zero; // True when tx0_phase should be reset to zero
 
 //generate if (VNA == 1) begin: VNA1
 
@@ -371,7 +372,7 @@ assign rx_data_q[0] = VNA_SCAN_FPGA ? vna_out_Q : rx0_out_Q;
 // This module is a replacement for receiver zero when the FPGA scans in VNA mode.
 vna_scanner #(.CICRATE(CICRATE), .RATE48(RATE48)) rx_vna (  // use this output for VNA_SCAN_FPGA
     //control
-    .clock(clk),
+    .clk(clk),
     .freq_delta(rx_phase[0]),
     .output_strobe(vna_strobe),
     //input
@@ -382,8 +383,9 @@ vna_scanner #(.CICRATE(CICRATE), .RATE48(RATE48)) rx_vna (  // use this output f
     .out_data_Q(vna_out_Q),
     // VNA mode data
     .vna(vna),
-    .Tx_frequency_in(tx_phase0),
-    .Tx_frequency_out(tx0_phase),
+    .tx_freq_in(tx_phase0),
+    .tx_freq(tx0_phase),
+    .tx_zero(tx0_phase_zero),
     .vna_count(vna_count)
     );
 
@@ -395,7 +397,7 @@ vna_scanner #(.CICRATE(CICRATE), .RATE48(RATE48)) rx_vna (  // use this output f
   mix2 #(.CALCTYPE(3)) mix2_0 (
     .clk(clk),
     .clk_2x(clk_2x),
-    .rst(1'b0),
+    .rst(&tx0_phase_zero),
     .phi0(rx0_phase),
     .phi1(rx_phase[2]),
     .adc(adcpipe[0]),