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Merge Pull Request #2405 from Anunalla/sst-elements/issue-fix
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Automatically Merged using SST Pull Request AutoTester
PR Title: b'Vanadis - Refactoring codebase to modularize instruction and LSQ definitions'
PR Author: Anunalla
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sst-autotester authored Oct 24, 2024
2 parents 37c64f6 + 90e3bef commit 68d41cb
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Showing 95 changed files with 4,252 additions and 2,977 deletions.
2 changes: 2 additions & 0 deletions src/sst/elements/vanadis/decoder/vdecoder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@
#include "vinsloader.h"
#include "vfpflags.h"


#include <cinttypes>
#include <cstdint>
#include <sst/core/interfaces/stdMem.h>
Expand Down Expand Up @@ -266,6 +267,7 @@ class VanadisDecoder : public SST::SubComponent
Statistic<uint64_t>* stat_ins_bytes_loaded;
};


} // namespace Vanadis
} // namespace SST

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127 changes: 77 additions & 50 deletions src/sst/elements/vanadis/decoder/vriscv64decoder.h
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90 changes: 57 additions & 33 deletions src/sst/elements/vanadis/inst/regfile.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,8 @@ class VanadisRegisterFile

public:
VanadisRegisterFile(
const uint32_t thr, const VanadisDecoderOptions* decoder_ots, const uint16_t int_regs, const uint16_t fp_regs,
const VanadisFPRegisterMode fp_rmode) :
const uint32_t thr, const VanadisDecoderOptions* decoder_ots, const uint16_t int_regs, const uint16_t fp_regs,
const VanadisFPRegisterMode fp_rmode, SST::Output* logger) :
hw_thread(thr),
count_int_regs(int_regs),
count_fp_regs(fp_regs),
Expand All @@ -43,10 +43,16 @@ class VanadisRegisterFile
fp_reg_width( (fp_rmode == VANADIS_REGISTER_MODE_FP32) ? 4 : 8 )
{
// Registers are always 64-bits

int_reg_storage = new char[int_reg_width * count_int_regs];
fp_reg_storage = new char[fp_reg_width * count_fp_regs];

init();
output = logger;

fpRegWidth_per_thread = fp_reg_width * count_fp_regs;
intRegWidth_per_thread = int_reg_width * count_int_regs;

}

void init( ) {
Expand All @@ -72,7 +78,7 @@ class VanadisRegisterFile

void copyFromRegister(uint16_t reg, uint32_t offset, uint8_t* values, uint32_t len, bool is_fp) {
if(is_fp) {
copyFromFPRegister(reg, offset, values, len);
copyFromFPRegister(reg, offset, values, len);
} else {
copyFromIntRegister(reg, offset, values, len);
}
Expand All @@ -81,9 +87,9 @@ class VanadisRegisterFile
void copyFromFPRegister(uint16_t reg, uint32_t offset, uint8_t* values, uint32_t len) {
assert(reg < count_fp_regs);
assert((offset + len) <= fp_reg_width);

uint8_t* reg_ptr = (uint8_t*) &fp_reg_storage[reg * fp_reg_width];

int index = get_reg_index(reg,1);
uint8_t* reg_ptr = (uint8_t*) &fp_reg_storage[index];
for(auto i = 0; i < len; ++i) {
values[i] = reg_ptr[offset + i];
}
Expand All @@ -92,27 +98,20 @@ class VanadisRegisterFile
void copyFromIntRegister(uint16_t reg, uint32_t offset, uint8_t* values, uint32_t len) {
assert(reg < count_int_regs);
assert((offset + len) <= int_reg_width);

uint8_t* reg_ptr = (uint8_t*) &int_reg_storage[reg * int_reg_width];

int index = get_reg_index(reg, 0);
uint8_t* reg_ptr = (uint8_t*) &int_reg_storage[index];
for(auto i = 0; i < len; ++i) {
values[i] = reg_ptr[offset + i];
}
}

void copyToRegister(uint16_t reg, uint32_t offset, uint8_t* values, uint32_t len, bool is_fp) {
if(is_fp) {
copyToFPRegister(reg, offset, values, len);
} else {
copyToIntRegister(reg, offset, values, len);
}

}

void copyToIntRegister(uint16_t reg, uint32_t offset, uint8_t* values, uint32_t len) {
assert((offset + len) <= int_reg_width);
assert(reg < count_int_regs);

uint8_t* reg_ptr = (uint8_t*) &int_reg_storage[reg * int_reg_width];
int index = get_reg_index(reg, 0);
uint8_t* reg_ptr = (uint8_t*) &int_reg_storage[index];
for(auto i = 0; i < len; ++i) {
reg_ptr[offset + i] = values[i];
}
Expand All @@ -121,8 +120,8 @@ class VanadisRegisterFile
void copyToFPRegister(uint16_t reg, uint32_t offset, uint8_t* values, uint32_t len) {
assert((offset + len) <= fp_reg_width);
assert(reg < count_fp_regs);

uint8_t* reg_ptr = (uint8_t*) &fp_reg_storage[reg * fp_reg_width];
int index = get_reg_index(reg, 1);
uint8_t* reg_ptr = (uint8_t*) &fp_reg_storage[index];
for(auto i = 0; i < len; ++i) {
reg_ptr[offset + i] = values[i];
}
Expand All @@ -134,8 +133,10 @@ class VanadisRegisterFile
assert(reg < count_int_regs);
assert(sizeof(T) <= int_reg_width);

if ( reg != decoder_opts->getRegisterIgnoreWrites() ) {
char* reg_start = &int_reg_storage[reg * int_reg_width];
if ( reg != decoder_opts->getRegisterIgnoreWrites() )
{
int index = get_reg_index(reg, 0);
char* reg_start = &int_reg_storage[index];
T* reg_start_T = (T*)reg_start;
return *(reg_start_T);
}
Expand All @@ -149,8 +150,8 @@ class VanadisRegisterFile
{
assert(reg < count_fp_regs);
assert(sizeof(T) <= fp_reg_width);

char* reg_start = &fp_reg_storage[reg * fp_reg_width];
int index = get_reg_index(reg, 1);
char* reg_start = &fp_reg_storage[index];
T* reg_start_T = (T*)reg_start;
return *(reg_start_T);
}
Expand All @@ -161,7 +162,8 @@ class VanadisRegisterFile
assert(reg < count_int_regs);

if ( LIKELY(reg != decoder_opts->getRegisterIgnoreWrites()) ) {
T* reg_ptr_t = (T*)(&int_reg_storage[int_reg_width * reg]);
int index = get_reg_index(reg, 0);
T* reg_ptr_t = (T*)(&int_reg_storage[index]);
char* reg_ptr_c = (char*)(reg_ptr_t);

reg_ptr_t[0] = val;
Expand All @@ -182,18 +184,21 @@ class VanadisRegisterFile
assert(sizeof(T) <= fp_reg_width);

uint8_t* val_ptr = (uint8_t*) &val;

int index = get_reg_index(reg, 1);
for(auto i = 0; i < sizeof(T); ++i) {
fp_reg_storage[fp_reg_width * reg + i] = val_ptr[i];
fp_reg_storage[index + i] = val_ptr[i];
}

// Pad with extra zeros if needed
for(auto i = sizeof(T); i < fp_reg_width; ++i) {
fp_reg_storage[fp_reg_width * reg + i] = 0;
fp_reg_storage[index + i] = 0;
}
}


uint32_t getHWThread() const { return hw_thread; }
uint16_t getThreadCount() const { return threadCount; }
void setThreadCount(uint16_t threads) { threadCount= threads; }
uint16_t countIntRegs() const { return count_int_regs; }
uint16_t countFPRegs() const { return count_fp_regs; }

Expand All @@ -216,13 +221,15 @@ class VanadisRegisterFile
char* getIntReg(const uint16_t reg)
{
assert(reg < count_int_regs);
return int_reg_storage + (int_reg_width * reg);
int index = get_reg_index(reg, 0);
return int_reg_storage + (index);
}

char* getFPReg(const uint16_t reg)
{
assert(reg < count_fp_regs);
return fp_reg_storage + (fp_reg_width * reg);
int index = get_reg_index(reg, 1);
return fp_reg_storage + (index);
}

void printRegister(SST::Output* output, bool isInt, uint16_t reg, int level = 8)
Expand Down Expand Up @@ -251,7 +258,18 @@ class VanadisRegisterFile
output->verbose(CALL_INFO, level, 0, "R[%5" PRIu16 "]: %s\n", reg, val_string);
delete[] val_string;
}


int get_reg_index(uint16_t reg, bool is_fp)
{
int index = 0;
if(is_fp) {
index = fp_reg_width * reg;
} else {
index = int_reg_width * reg;
}
return index;

}
const uint32_t hw_thread;
const uint16_t count_int_regs;
const uint16_t count_fp_regs;
Expand All @@ -263,6 +281,12 @@ class VanadisRegisterFile
VanadisFPRegisterMode fp_reg_mode;
const uint32_t fp_reg_width;
const uint32_t int_reg_width;

int fpRegWidth_per_thread;
int intRegWidth_per_thread;
SST::Output* output;
uint16_t threadCount;

};

} // namespace Vanadis
Expand Down
96 changes: 46 additions & 50 deletions src/sst/elements/vanadis/inst/vadd.h
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Original file line number Diff line number Diff line change
Expand Up @@ -21,64 +21,60 @@
namespace SST {
namespace Vanadis {


template <typename gpr_format>
class VanadisAddInstruction : public VanadisInstruction
class VanadisAddInstruction : public virtual VanadisInstruction
{
public:
VanadisAddInstruction(
const uint64_t addr, const uint32_t hw_thr, const VanadisDecoderOptions* isa_opts, const uint16_t dest,
const uint16_t src_1, const uint16_t src_2) :
VanadisInstruction(addr, hw_thr, isa_opts, 2, 1, 2, 1, 0, 0, 0, 0)
{

isa_int_regs_in[0] = src_1;
isa_int_regs_in[1] = src_2;
isa_int_regs_out[0] = dest;
}

VanadisAddInstruction* clone() override { return new VanadisAddInstruction(*this); }
VanadisFunctionalUnitType getInstFuncType() const override { return INST_INT_ARITH; }

const char* getInstCode() const override
{
if(sizeof(gpr_format) == 8) {
return "ADD64";
} else {
return "ADD32";
}
}

void printToBuffer(char* buffer, size_t buffer_size) override
{
snprintf(
buffer, buffer_size,
"%s %5" PRIu16 " <- %5" PRIu16 " + %5" PRIu16 " (phys: %5" PRIu16 " <- %5" PRIu16 " + %5" PRIu16 ")",
getInstCode(), isa_int_regs_out[0], isa_int_regs_in[0], isa_int_regs_in[1], phys_int_regs_out[0],
phys_int_regs_in[0], phys_int_regs_in[1]);
}

void execute(SST::Output* output, VanadisRegisterFile* regFile) override
{
#ifdef VANADIS_BUILD_DEBUG
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0,
"Execute: 0x%" PRI_ADDR " %s phys: out=%" PRIu16 " in=%" PRIu16 ", %" PRIu16 ", isa: out=%" PRIu16
" / in=%" PRIu16 ", %" PRIu16 "\n",
getInstructionAddress(), getInstCode(), phys_int_regs_out[0], phys_int_regs_in[0],
phys_int_regs_in[1], isa_int_regs_out[0], isa_int_regs_in[0], isa_int_regs_in[1]);
public:
VanadisAddInstruction(const uint64_t addr, const uint32_t hw_thr,
const VanadisDecoderOptions* isa_opts, const uint16_t dest,
const uint16_t src_1, const uint16_t src_2) :
VanadisInstruction(addr, hw_thr, isa_opts, 2, 1, 2, 1, 0, 0, 0, 0)
{

isa_int_regs_in[0] = src_1;
isa_int_regs_in[1] = src_2;
isa_int_regs_out[0] = dest;
}

VanadisAddInstruction* clone() override { return new VanadisAddInstruction(*this); }
VanadisFunctionalUnitType getInstFuncType() const override { return INST_INT_ARITH; }

const char* getInstCode() const override
{
if(sizeof(gpr_format) == 8) {
return "ADD64";
} else {
return "ADD32";
}
}
#endif

const gpr_format src_1 = regFile->getIntReg<gpr_format>(phys_int_regs_in[0]);
const gpr_format src_2 = regFile->getIntReg<gpr_format>(phys_int_regs_in[1]);
void printToBuffer(char* buffer, size_t buffer_size) override
{
snprintf(
buffer, buffer_size,
"%s %5" PRIu16 " <- %5" PRIu16 " + %5" PRIu16 " (phys: %5" PRIu16 " <- %5" PRIu16 " + %5" PRIu16 ")",
getInstCode(), isa_int_regs_out[0], isa_int_regs_in[0], isa_int_regs_in[1], phys_int_regs_out[0],
phys_int_regs_in[0], phys_int_regs_in[1]);
}



regFile->setIntReg<gpr_format>(phys_int_regs_out[0], src_1 + src_2);
void instOp(VanadisRegisterFile* regFile,
uint16_t phys_int_regs_out_0, uint16_t phys_int_regs_in_0,
uint16_t phys_int_regs_in_1)
{
const gpr_format src_1 = regFile->getIntReg<gpr_format>(phys_int_regs_in_0);
const gpr_format src_2 = regFile->getIntReg<gpr_format>(phys_int_regs_in_1);
regFile->setIntReg<gpr_format>(phys_int_regs_out_0,src_1+src_2);
}

markExecuted();
}

};




} // namespace Vanadis
} // namespace SST

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