Merge pull request #1732 from sstsimulator/devel

Automatically Merged using SST Master Branch Merger

src/sst/elements/balar/Makefile.am

@@ -8,9 +8,21 @@ comp_LTLIBRARIES = libbalar.la
 libbalar_la_SOURCES = \
 	mempool.h \
 	mempool.cpp \
+	balar_event.h \
+	cuda_runtime_api.h \
 	balar.cc \
 	balar.h
 
+EXTRA_DIST = \
+	tests/ariel-gpu-v100.cfg \
+	tests/cuda-test.py \
+	tests/gpgpusim.config \
+	tests/testsuite_default_balar.py \
+	tests/utils.py \
+	tests/vectorAdd/vecAdd.cu \
+	tests/vectorAdd/Makefile \
+	tests/refFiles/test_gpgpu_vectorAdd.out
+
 libbalar_la_CPPFLAGS = \
 	-I$(top_srcdir)/src \
 	$(SST_CXX0X_FLAGS) -fPIC -Wall \

src/sst/elements/memHierarchy/memNIC.cc

@@ -109,7 +109,7 @@ void MemNIC::send(MemEventBase *ev) {
     req->vn = 0;
 
     if (is_debug_event(ev)) {
-        dbg.debug(_L5_, "N: %-40" PRIu64 "  %-20s Enqueue       Dst: %u, bits: %zu, (%s)\n", 
+        dbg.debug(_L5_, "N: %-40" PRIu64 "  %-20s Enqueue       Dst: %lld, bits: %zu, (%s)\n", 
             Simulation::getSimulation()->getCurrentSimCycle(), getName().c_str(), req->dest, req->size_in_bits, ev->getBriefString().c_str());
     }
 

src/sst/elements/memHierarchy/memNIC.h

@@ -74,7 +74,7 @@ class MemNIC : public MemNICBase {
     virtual ~MemNIC() { }
 
     /* Functions called by parent for handling events */
-    void send(MemEventBase * ev);
+    void send(MemEventBase * ev) override;
     MemEventBase * recv();
     bool isClocked() override { return false; }
 
@@ -89,13 +89,13 @@ class MemNIC : public MemNICBase {
     size_t getSizeInBits(MemEventBase * ev);
 
     /* Initialization and finish */
-    void init(unsigned int phase);
-    void finish() { link_control->finish(); }
-    void setup() { link_control->setup(); MemNICBase::setup(); }
+    void init(unsigned int phase) override;
+    void finish() override { link_control->finish(); }
+    void setup() override { link_control->setup(); MemNICBase::setup(); }
 
     /* Debug */
-    void printStatus(Output &out);
-    void emergencyShutdownDebug(Output &out);
+    void printStatus(Output &out) override;
+    void emergencyShutdownDebug(Output &out) override;
 
 private:
 

src/sst/elements/memHierarchy/testcpu/standardCPU.cc

@@ -50,7 +50,8 @@ standardCPU::standardCPU(ComponentId_t id, Params& params) :
     /* Required parameter - memSize */
     UnitAlgebra memsize = params.find<UnitAlgebra>("memSize", UnitAlgebra("0B"), found);
     if ( !found ) {
-        out.fatal(CALL_INFO, -1, "%s, Error: parameter 'memSize' was not provided\n");
+        out.fatal(CALL_INFO, -1, "%s, Error: parameter 'memSize' was not provided\n",
+                getName().c_str());
     }
     if (!(memsize.hasUnits("B"))) {
         out.fatal(CALL_INFO, -1, "%s, Error: memSize parameter requires units of 'B' (SI OK). You provided '%s'\n",
@@ -267,7 +268,7 @@ StandardMem::Request* standardCPU::createWrite(Addr addr) {
         req->setNoncacheable();
         noncacheableWrites->addData(1);
     }
-    out.verbose(CALL_INFO, 2, 0, "%s: %d Issued %sWrite for address 0x%" PRIx64 "\n", getName().c_str(), ops, req->getNoncacheable() ? "Noncacheable " : "", addr);
+    out.verbose(CALL_INFO, 2, 0, "%s: %" PRIu64 " Issued %sWrite for address 0x%" PRIx64 "\n", getName().c_str(), ops, req->getNoncacheable() ? "Noncacheable " : "", addr);
     return req;
 }
 
@@ -279,7 +280,7 @@ StandardMem::Request* standardCPU::createRead(Addr addr) {
         req->setNoncacheable();
         noncacheableReads->addData(1);
     }
-    out.verbose(CALL_INFO, 2, 0, "%s: %d Issued %sRead for address 0x%" PRIx64 "\n", getName().c_str(), ops, req->getNoncacheable() ? "Noncacheable " : "", addr);
+    out.verbose(CALL_INFO, 2, 0, "%s: %" PRIu64 " Issued %sRead for address 0x%" PRIx64 "\n", getName().c_str(), ops, req->getNoncacheable() ? "Noncacheable " : "", addr);
     return req;
 }
 
@@ -290,7 +291,7 @@ StandardMem::Request* standardCPU::createFlush(Addr addr) {
     addr = addr - (addr % lineSize);
     StandardMem::Request* req = new Experimental::Interfaces::StandardMem::FlushAddr(addr, lineSize, false, 10);
     num_flushes_issued->addData(1);
-    out.verbose(CALL_INFO, 2, 0, "%s: %d Issued FlushAddr for address 0x%" PRIx64 "\n", getName().c_str(), ops,  addr);
+    out.verbose(CALL_INFO, 2, 0, "%s: %" PRIu64 " Issued FlushAddr for address 0x%" PRIx64 "\n", getName().c_str(), ops,  addr);
     return req;
 }
 
@@ -301,7 +302,7 @@ StandardMem::Request* standardCPU::createFlushInv(Addr addr) {
     addr = addr - (addr % lineSize);
     StandardMem::Request* req = new Experimental::Interfaces::StandardMem::FlushAddr(addr, lineSize, true, 10);
     num_flushinvs_issued->addData(1);
-    out.verbose(CALL_INFO, 2, 0, "%s: %d Issued FlushAddrInv for address 0x%" PRIx64 "\n", getName().c_str(), ops,  addr);
+    out.verbose(CALL_INFO, 2, 0, "%s: %" PRIu64 " Issued FlushAddrInv for address 0x%" PRIx64 "\n", getName().c_str(), ops,  addr);
     return req;
 }
 
@@ -320,7 +321,7 @@ StandardMem::Request* standardCPU::createLL(Addr addr) {
     ll_addr = addr;
     ll_issued = true;
 
-    out.verbose(CALL_INFO, 2, 0, "%s: %d Issued LoadLink for address 0x%" PRIx64 "\n", getName().c_str(), ops, addr);
+    out.verbose(CALL_INFO, 2, 0, "%s: %" PRIu64 " Issued LoadLink for address 0x%" PRIx64 "\n", getName().c_str(), ops, addr);
     return req;
 }
 
@@ -334,7 +335,7 @@ StandardMem::Request* standardCPU::createSC() {
     StandardMem::Request* req = new Experimental::Interfaces::StandardMem::StoreConditional(ll_addr, data.size(), data);
     num_llsc_issued->addData(1);
     ll_issued = false;
-    out.verbose(CALL_INFO, 2, 0, "%s: %d Issued StoreConditional for address 0x%" PRIx64 "\n", getName().c_str(), ops, ll_addr);
+    out.verbose(CALL_INFO, 2, 0, "%s: %" PRIu64 " Issued StoreConditional for address 0x%" PRIx64 "\n", getName().c_str(), ops, ll_addr);
     return req;
 }
 
@@ -349,13 +350,13 @@ StandardMem::Request* standardCPU::createMMIOWrite() {
         payload >>=8;
     }
     StandardMem::Request* req = new Experimental::Interfaces::StandardMem::Write(mmioAddr, sizeof(int32_t), data, posted);
-    out.verbose(CALL_INFO, 2, 0, "%s: %d Issued MMIO Write for address 0x%" PRIx64 " with payload %d\n", getName().c_str(), ops, mmioAddr, payload_cp);
+    out.verbose(CALL_INFO, 2, 0, "%s: %" PRIu64 " Issued MMIO Write for address 0x%" PRIx64 " with payload %d\n", getName().c_str(), ops, mmioAddr, payload_cp);
     return req;
 }
 
 StandardMem::Request* standardCPU::createMMIORead() {
     StandardMem::Request* req = new Experimental::Interfaces::StandardMem::Read(mmioAddr, sizeof(int32_t));
-    out.verbose(CALL_INFO, 2, 0, "%s: %d Issued MMIO Read for address 0x%" PRIx64 "\n", getName().c_str(), ops, mmioAddr);
+    out.verbose(CALL_INFO, 2, 0, "%s: %" PRIu64 " Issued MMIO Read for address 0x%" PRIx64 "\n", getName().c_str(), ops, mmioAddr);
     return req;
 }
 

src/sst/elements/memHierarchy/testcpu/standardMMIO.cc

@@ -73,7 +73,8 @@ StandardMMIO::StandardMMIO(ComponentId_t id, Params &params) : SST::Component(id
         bool found;
         max_addr = params.find<Addr>("max_addr", 0, found);
         if (!found) {
-            out.fatal(CALL_INFO, 0-1, "%s, Error: Invalid param, 'max_addr' must be specified if mem_accesses > 0\n");
+            out.fatal(CALL_INFO, -1, "%s, Error: Invalid param, 'max_addr' must be specified if mem_accesses > 0\n", 
+                    getName().c_str());
         }
 
         // Register related statistics

src/sst/elements/vanadis/inst/vaddi.h

@@ -32,7 +32,7 @@ class VanadisAddImmInstruction : public VanadisInstruction {
         isa_int_regs_out[0] = dest;
     }
 
-    VanadisAddImmInstruction* clone() { return new VanadisAddImmInstruction(*this); }
+    VanadisAddImmInstruction* clone() override { return new VanadisAddImmInstruction(*this); }
     VanadisFunctionalUnitType getInstFuncType() const override { return INST_INT_ARITH; }
     const char* getInstCode() const override { return "ADDI"; }
 

src/sst/elements/vanadis/inst/vandi.h

@@ -33,7 +33,7 @@ class VanadisAndImmInstruction : public VanadisInstruction {
 
     VanadisAndImmInstruction* clone() override { return new VanadisAndImmInstruction(*this); }
     VanadisFunctionalUnitType getInstFuncType() const override { return INST_INT_ARITH; }
-    const char* getInstCode() const { return "ANDI"; }
+    const char* getInstCode() const override { return "ANDI"; }
 
     void printToBuffer(char* buffer, size_t buffer_size) override {
         snprintf(

src/sst/elements/vanadis/inst/vfpscmp.h

@@ -54,11 +54,11 @@ class VanadisFPSetRegCompareInstruction : public VanadisInstruction {
         }
     }
 
-    VanadisFPSetRegCompareInstruction* clone() { return new VanadisFPSetRegCompareInstruction(*this); }
+    VanadisFPSetRegCompareInstruction* clone() override { return new VanadisFPSetRegCompareInstruction(*this); }
 
-    virtual VanadisFunctionalUnitType getInstFuncType() const { return INST_FP_ARITH; }
+    virtual VanadisFunctionalUnitType getInstFuncType() const override { return INST_FP_ARITH; }
 
-    virtual const char* getInstCode() const {
+    virtual const char* getInstCode() const override {
         switch (register_format) {
         case VanadisRegisterFormat::VANADIS_FORMAT_FP64: {
             switch (compare_type) {

src/sst/elements/vanadis/inst/vsrli.h

@@ -43,7 +43,7 @@ class VanadisShiftRightLogicalImmInstruction : public VanadisInstruction {
     VanadisFunctionalUnitType getInstFuncType() const override { return INST_INT_ARITH; }
     const char* getInstCode() const override { return "SRLI"; }
 
-    void printToBuffer(char* buffer, size_t buffer_size) {
+    void printToBuffer(char* buffer, size_t buffer_size) override {
         snprintf(buffer, buffer_size,
                  "SRLI    %5" PRIu16 " <- %5" PRIu16 " >> imm=%" PRId64 " (phys: %5" PRIu16 " <- %5" PRIu16
                  " >> %" PRId64 ")",