Add regression test for connecting module output port to array variab…

…le (issue #1001).

ivtest/ivltests/br_gh1001.v

@@ -0,0 +1,22 @@
+module dut(output logic [7:0] op[1:0]);
+
+assign op[0] = 8'd1;
+assign op[1] = 8'd2;
+
+endmodule
+
+module test();
+
+logic [7:0] v[1:0];
+
+dut dut(v);
+
+initial begin
+  #0 $display("%b %b", v[0], v[1]);
+  if ((v[0] === 8'd1) && (v[1] === 8'd2))
+    $display("PASSED");
+  else
+    $display("FAILED");
+end
+
+endmodule

ivtest/regress-vvp.list

@@ -31,6 +31,7 @@ br_gh710a			vvp_tests/br_gh710a.json
 br_gh710b			vvp_tests/br_gh710b.json
 br_gh710c			vvp_tests/br_gh710c.json
 br_gh939			vvp_tests/br_gh939.json
+br_gh1001			vvp_tests/br_gh1001.json
 br_gh1018			vvp_tests/br_gh1018.json
 br_gh1029			vvp_tests/br_gh1029.json
 br_gh1075a			vvp_tests/br_gh1074a.json

ivtest/vvp_tests/br_gh1001.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "br_gh1001.v",
+    "iverilog-args" : [ "-g2009" ]
+}