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Add regression test for issue #1122.
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module tranif_or(a, b, y); | ||
input a, b; | ||
inout y; | ||
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supply1 vdd; | ||
supply0 vss; | ||
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wire w1, w2; | ||
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// NOR | ||
tranif0(w1, vdd, a); | ||
tranif0(w2, w1, b); | ||
tranif1(w2, vss, a); | ||
tranif1(w2, vss, b); | ||
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// OR | ||
tranif0(y, vdd, w2); | ||
tranif1(y, vss, w2); | ||
endmodule | ||
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module test; | ||
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reg a, b; | ||
wire y; | ||
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tranif_or dut(a, b, y); | ||
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reg failed = 0; | ||
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initial begin | ||
$monitor("%t a=%b b=%b Y=%b", $time, a, b, y); | ||
#10 a = 0; b = 0; | ||
#0 if (y !== 0) failed = 1; | ||
#10 a = 0; b = 1; | ||
#0 if (y !== 1) failed = 1; | ||
#10 a = 1; b = 0; | ||
#0 if (y !== 1) failed = 1; | ||
#10 a = 1; b = 1; | ||
#0 if (y !== 1) failed = 1; | ||
#1; | ||
if (failed) | ||
$display("FAILED"); | ||
else | ||
$display("PASSED"); | ||
end | ||
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endmodule | ||
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{ | ||
"type" : "normal", | ||
"source" : "br_gh1122.v" | ||
} |