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Aligned naming for flash and option bytes #defines
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@Nightwalker-87
Nightwalker-87 committed Jan 12, 2025
1 parent b9bef5c commit ed5ea0d
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Showing 55 changed files with 722 additions and 722 deletions.
2 changes: 1 addition & 1 deletion config/chips/C011xx.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x1800 // 6 KB
bootrom_base 0x1fff0000
bootrom_size 0x1800 // 6 KB
option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_C0
option_size 0x80 // 128 B
flags none
2 changes: 1 addition & 1 deletion config/chips/C031xx.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x3000 // 12 KB
bootrom_base 0x1fff0000
bootrom_size 0x1800 // 6 KB
option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_C0
option_size 0x80 // 128 B
flags none
2 changes: 1 addition & 1 deletion config/chips/C051xx.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x3000 // 12 KB
bootrom_base 0x1fff0000
bootrom_size 0x1800 // 6 KB
option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_C0
option_size 0x80 // 128 B
flags none
2 changes: 1 addition & 1 deletion config/chips/C071xx.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x6000 // 24 KB
bootrom_base 0x1fff0000
bootrom_size 0x1800 // 6 KB
option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_C0
option_size 0x80 // 128 B
flags none
2 changes: 1 addition & 1 deletion config/chips/C091xx.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x9000 // 36 KB: C92xx: 30 KB + 6KB FDCAN RAM (RM490 rev. 5 2.4 FDCAN RAM)
bootrom_base 0x1fff0000
bootrom_size 0x1800 // 6 KB
option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_C0
option_size 0x80 // 128 B
flags none
2 changes: 1 addition & 1 deletion config/chips/F03x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x400 // 1 KB
sram_size 0x1000 // 4 KB
bootrom_base 0x1fffec00
bootrom_size 0xc00 // 3 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags none
2 changes: 1 addition & 1 deletion config/chips/F04x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x400 // 1 KB
sram_size 0x1800 // 6 KB
bootrom_base 0x1fffec00
bootrom_size 0xc00 // 3 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags none
2 changes: 1 addition & 1 deletion config/chips/F05x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x400 // 1 KB
sram_size 0x2000 // 8 KB
bootrom_base 0x1fffec00
bootrom_size 0xc00 // 3 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags none
2 changes: 1 addition & 1 deletion config/chips/F07x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x4000 // 16 KB
bootrom_base 0x1fffc800
bootrom_size 0x3000 // 12 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags none
2 changes: 1 addition & 1 deletion config/chips/F09x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x8000 // 32 KB
bootrom_base 0x1fffd800
bootrom_size 0x2000 // 8 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags none
2 changes: 1 addition & 1 deletion config/chips/F1xx_CL.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x10000 // 64 KB
bootrom_base 0x1fffb000
bootrom_size 0x4800 // 18 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F1xx_HD.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x10000 // 64 KB
bootrom_base 0x1ffff000
bootrom_size 0x800 // 2 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F1xx_LD.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x400 // 1 KB
sram_size 0x2800 // 10 KB
bootrom_base 0x1ffff000
bootrom_size 0x800 // 2 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F1xx_MD.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x400 // 1 KB
sram_size 0x5000 // 20 KB
bootrom_base 0x1ffff000
bootrom_size 0x800 // 2 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F1xx_VL_HD.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x8000 // 32 KB
bootrom_base 0x1ffff000
bootrom_size 0x800 // 2 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F1xx_VL_MD_LD.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x400 // 1 KB
sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */
bootrom_base 0x1ffff000
bootrom_size 0x800 // 2 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F1xx_XLD.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x18000 // 96 KB
bootrom_base 0x1fffe000
bootrom_size 0x1800 // 6 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F2xx.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x20000 // 128 KB
sram_size 0x20000 // 128 KB
bootrom_base 0x1fff0000
bootrom_size 0x7800 // 30 KB
option_base 0x1fffc000 // STM32_F2_OPTION_BYTES_BASE
option_base 0x1fffc000 // STM32_OPTION_BYTES_BASE_F2
option_size 0x4 // 4 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F301_F302_F318.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0xa000 // 40 KB
bootrom_base 0x1fffd800
bootrom_size 0x2000 // 8 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F302_F303_F358.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0xa000 // 40 KB
bootrom_base 0x1ffff000
bootrom_size 0x800 // 2 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F302_F303_F398_HD.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x10000 // 64 KB
bootrom_base 0x1fffd800
bootrom_size 0x2000 // 8 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F303_F328_F334.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x3000 // 12 KB
bootrom_base 0x1fffd800
bootrom_size 0x2000 // 8 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F37x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0xa000 // 40 KB
bootrom_base 0x1ffff000
bootrom_size 0x800 // 2 KB
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_F0
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F401xD_xE.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x4000 // 16 KB
sram_size 0x18000 // 96 KB
bootrom_base 0x1fff0000
bootrom_size 0x7800 // 30 KB
option_base 0x40023C14 // STM32_F4_OPTION_BYTES_BASE
option_base 0x40023C14 // STM32_OPTION_BYTES_BASE_F4
option_size 0x4 // 4 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F446.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x20000 // 128 KB
sram_size 0x20000 // 128 KB
bootrom_base 0x1fff0000
bootrom_size 0x7800 // 30 KB
option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE
option_base 0x40023c14 // STM32_OPTION_BYTES_BASE_F4
option_size 0x10 // 16 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F4x5_F4x7.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x4000 // 16 KB
sram_size 0x30000 // 192 KB
bootrom_base 0x1fff0000
bootrom_size 0x7800 // 30 KB
option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE
option_base 0x40023c14 // STM32_OPTION_BYTES_BASE_F4
option_size 0x4 // 4 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F72x_F73x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x40000 // 256 KB
bootrom_base 0x100000
bootrom_size 0xedc0 // 59.4375 KB
option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE
option_base 0x1fff0000 // STM32_OPTION_BYTES_BASE_F7
option_size 0x20 // 32 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F74x_F75x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x50000 // 320 KB
bootrom_base 0x100000
bootrom_size 0xedc0 // 59.4375 KB
option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE
option_base 0x1fff0000 // STM32_OPTION_BYTES_BASE_F7
option_size 0x20 // 32 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/F76x_F77x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x80000 // 512 KB
bootrom_base 0x200000
bootrom_size 0xedc0 // 59.4375 KB
option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE /* Used for reading back option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 */
option_base 0x1fff0000 // STM32_OPTION_BYTES_BASE_F7 /* Used for reading back option bytes, writing uses STM32_FLASH_F7_OPTCR and STM32_FLASH_F7_OPTCR1 */
option_size 0x20 // 32 B
flags swo dualbank
2 changes: 1 addition & 1 deletion config/chips/G03x_G04x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x2000 // 8 KB
bootrom_base 0x1fff0000
bootrom_size 0x2000 // 8 KB
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_G0
option_size 0x80 // 128 B
flags none
2 changes: 1 addition & 1 deletion config/chips/G05x_G06x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x4800 // 18 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_G0
option_size 0x80 // 128 B
flags none
2 changes: 1 addition & 1 deletion config/chips/G07x_G08x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x9000 // 36 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_G0
option_size 0x80 // 128 B
flags none
2 changes: 1 addition & 1 deletion config/chips/G0Bx_G0Cx.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x24000 // 144 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_G0
option_size 0x80 // 128 B
flags dualbank
2 changes: 1 addition & 1 deletion config/chips/G43x_G44x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x8000 // 32 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_G4
option_size 0x4 // 4 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/G47x_G48x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x20000 // 128 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_G4
option_size 0x4 // 4 B
flags swo dualbank
2 changes: 1 addition & 1 deletion config/chips/G49x_G4Ax.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x1c000 // 112 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE
option_base 0x1ffff800 // STM32_OPTION_BYTES_BASE_G4
option_size 0x4 // 4 B
flags swo dualbank
2 changes: 1 addition & 1 deletion config/chips/H72x_H73x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x20000 // 128 KB
sram_size 0x20000 // 128 KB "DTCM"
bootrom_base 0x1ff00000
bootrom_size 0x20000 // 128 KB
option_base 0x52002020 // STM32_H7_OPTION_BYTES_BASE
option_base 0x52002020 // STM32_OPTION_BYTES_BASE_H7
option_size 0x2c // 44 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/H74x_H75x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x20000 // 128 KB
sram_size 0x20000 // 128 KB "DTCM"
bootrom_base 0x1ff00000
bootrom_size 0x20000 // 128 KB
option_base 0x52002020 // STM32_H7_OPTION_BYTES_BASE
option_base 0x52002020 // STM32_OPTION_BYTES_BASE_H7
option_size 0x2c // 44 B /* FLASH_OPTSR_CUR to FLASH_BOOT_PRGR */
flags swo dualbank
2 changes: 1 addition & 1 deletion config/chips/H7Ax_H7Bx.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x20000 // 128 KB
sram_size 0x20000 // 128 KB "DTCM"
bootrom_base 0x1ff00000
bootrom_size 0x20000 // 128 KB
option_base 0x52002020 // STM32_H7_OPTION_BYTES_BASE
option_base 0x52002020 // STM32_OPTION_BYTES_BASE_H7
option_size 0x2c // 44 B
flags swo dualbank
2 changes: 1 addition & 1 deletion config/chips/L0xxx_Cat_1.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x80 // 128 B
sram_size 0x2000 // 8 KB
bootrom_base 0x1ff00000
bootrom_size 0x2000 // 8 KB
option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE
option_base 0x1ff80000 // STM32_OPTION_BYTES_BASE_L0
option_size 0x20 // 32 B
flags none
2 changes: 1 addition & 1 deletion config/chips/L0xxx_Cat_2.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x80 // 128 B
sram_size 0x2000 // 8 KB
bootrom_base 0x1ff00000
bootrom_size 0x1000 // 4 KB
option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE
option_base 0x1ff80000 // STM32_OPTION_BYTES_BASE_L0
option_size 0x20 // 32 B
flags none
2 changes: 1 addition & 1 deletion config/chips/L0xxx_Cat_3.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x80 // 128 B
sram_size 0x2000 // 8 KB
bootrom_base 0x1ff00000
bootrom_size 0x1000 // 4 KB
option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE
option_base 0x1ff80000 // STM32_OPTION_BYTES_BASE_L0
option_size 0x20 // 32 B
flags none
2 changes: 1 addition & 1 deletion config/chips/L0xxx_Cat_5.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x80 // 128 B
sram_size 0x5000 // 20 KB
bootrom_base 0x1ff00000
bootrom_size 0x2000 // 8 KB
option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE
option_base 0x1ff80000 // STM32_OPTION_BYTES_BASE_L0
option_size 0x20 // 32 B
flags dualbank
2 changes: 1 addition & 1 deletion config/chips/L1xx_Cat_4.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x100 // 128 B
sram_size 0xc000 // 48 KB
bootrom_base 0x1ff00000
bootrom_size 0x1000 // 4 KB
option_base 0x1ff80000 // STM32_L1_OPTION_BYTES_BASE
option_base 0x1ff80000 // STM32_OPTION_BYTES_BASE_L1
option_size 0x8 // 8 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/L41x_L42x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0xa000 // 40 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_L4
option_size 0x4 // 4 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/L43x_L44x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0xc000 // 48 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_L4
option_size 0x4 // 4 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/L47x_L48x.chip
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Expand Up @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x18000 // 96 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_L4
option_size 0x4 // 4 B
flags swo
2 changes: 1 addition & 1 deletion config/chips/L496x_L4A6x.chip
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Expand Up @@ -9,7 +9,7 @@ flash_pagesize 0x800 // 2 KB
sram_size 0x50000 // 320 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE
option_base 0x1fff7800 // STM32_OPTION_BYTES_BASE_L4
option_size 0x4 // 4 B
flags swo
otp_base 0x1fff7000
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