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Signed-off-by: Sébastien NEDJAR <[email protected]> Co-authored-by: Frederic Pillon <[email protected]>
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| transport select swd | ||
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| set ENABLE_LOW_POWER 1 | ||
| set STOP_WATCHDOG 1 | ||
| set CLOCK_FREQ 4000 | ||
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| reset_config none separate | ||
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| set CONNECT_UNDER_RESET 1 |
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variants/STM32WBxx/WB55R(C-E-G)V/variant_STEAM32_WB55RG.cpp
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| /* | ||
| ******************************************************************************* | ||
| * Copyright (c) 2021, STMicroelectronics | ||
| * All rights reserved. | ||
| * | ||
| * This software component is licensed by ST under BSD 3-Clause license, | ||
| * the "License"; You may not use this file except in compliance with the | ||
| * License. You may obtain a copy of the License at: | ||
| * opensource.org/licenses/BSD-3-Clause | ||
| * | ||
| ******************************************************************************* | ||
| */ | ||
| #include "variant_STEAM32_WB55RG.h" | ||
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| #if defined(ARDUINO_STEAM32_WB55RG) | ||
| #include "lock_resource.h" | ||
| #include "pins_arduino.h" | ||
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| // Pin number | ||
| const PinName digitalPin[] = { | ||
| PC_4, // P0/D0/A1 | ||
| PA_5, // P1/D1/A3 | ||
| PC_5, // P2/D2/A5 | ||
| PA_2, // P3/D3/A0 | ||
| PA_4, // P4/D4/A2 | ||
| PA_7, // P5/D5 | ||
| PC_3, // P6/D6 | ||
| PA_9, // P7/D7 | ||
| PA_15, // P8/D8 | ||
| PC_2, // P9/D9 | ||
| PA_6, // P10/D10/A4 | ||
| PA_8, // P11/D11 | ||
| PC_6, // P12/D12 | ||
| PB_13, // P13/D13 | ||
| PB_14, // P14/D14 | ||
| PB_15, // P15/D15 | ||
| PE_4, // P16/D16 | ||
| PC_0, // P19/D17 | ||
| PC_1, // P20/D18 | ||
| PB_2, // D19 | ||
| PD_0, // D20 | ||
| PB_8, // D21 | ||
| PB_9, // D22 | ||
| PC_13, // D23 | ||
| PB_12, // D24 | ||
| PB_0, // D25 | ||
| PD_1, // D26 | ||
| PB_6, // D27 | ||
| PB_7, // D28 | ||
| PC_10, // D29 | ||
| PH_3, // D30 | ||
| PC_11, // D31 | ||
| PC_12, // D32 | ||
| PA_0, // D33 | ||
| PA_3, // D34 | ||
| PA_10, // D35 | ||
| PA_12, // D36 | ||
| PB_1, // D37 | ||
| PB_10, // D38 | ||
| PB_11, // D39 | ||
| PA_11, // D40 | ||
| PB_4, // D41 | ||
| PB_5, // D42 | ||
| PA_1, // D43 | ||
| }; | ||
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| // Analog (Ax) pin number array | ||
| const uint32_t analogInputPin[] = { | ||
| 3, // A0 | ||
| 0, // A1 | ||
| 4, // A2 | ||
| 1, // A3 | ||
| 10, // A4 | ||
| 2 // A5 | ||
| }; | ||
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| // ---------------------------------------------------------------------------- | ||
| #ifdef __cplusplus | ||
| extern "C" { | ||
| #endif | ||
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| /** | ||
| * @brief System Clock Configuration | ||
| * @param None | ||
| * @retval None | ||
| */ | ||
| WEAK void SystemClock_Config(void) | ||
| { | ||
| RCC_OscInitTypeDef RCC_OscInitStruct = {}; | ||
| RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; | ||
| RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; | ||
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| /* This prevents concurrent access to RCC registers by CPU2 (M0+) */ | ||
| hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY); | ||
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| __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); | ||
| __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); | ||
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| /* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */ | ||
| hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY); | ||
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| /* Initializes the CPU, AHB and APB busses clocks */ | ||
| RCC_OscInitStruct.OscillatorType = | ||
| RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; | ||
| RCC_OscInitStruct.HSEState = RCC_HSE_ON; | ||
| RCC_OscInitStruct.LSEState = RCC_LSE_ON; | ||
| RCC_OscInitStruct.HSIState = RCC_HSI_ON; | ||
| RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; | ||
| RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; | ||
| RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; | ||
| RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; | ||
| RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; | ||
| RCC_OscInitStruct.PLL.PLLN = 16; | ||
| RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; | ||
| RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; | ||
| RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; | ||
| if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { | ||
| Error_Handler(); | ||
| } | ||
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| /* Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */ | ||
| RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK | | ||
| RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; | ||
| RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; | ||
| RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; | ||
| RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; | ||
| RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; | ||
| RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1; | ||
| RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; | ||
| if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { | ||
| Error_Handler(); | ||
| } | ||
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| /* Initializes the peripherals clocks */ | ||
| /* RNG needs to be configured like in M0 core, i.e. with HSI48 */ | ||
| PeriphClkInitStruct.PeriphClockSelection = | ||
| RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB; | ||
| PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; | ||
| PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; | ||
| PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE; | ||
| PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE; | ||
| PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1; | ||
| if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { | ||
| Error_Handler(); | ||
| } | ||
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| LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA); | ||
| LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40); | ||
| LL_PWR_SMPS_Enable(); | ||
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| /* Select HSI as system clock source after Wake Up from Stop mode */ | ||
| LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI); | ||
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| hsem_unlock(CFG_HW_RCC_SEMID); | ||
| } | ||
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| #ifdef __cplusplus | ||
| } | ||
| #endif | ||
| #endif /* ARDUINO_STEAM32_WB55RG */ |
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