[vivado_ip] remove XIP

stnolting · Feb 1, 2025 · 87758d1 · 87758d1
1 parent 80e491c
commit 87758d1
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diff --git a/rtl/system_integration/neorv32_vivado_ip.tcl b/rtl/system_integration/neorv32_vivado_ip.tcl
@@ -124,7 +124,6 @@ proc setup_ip_gui {} {
   set_property enablement_dependency {$IO_SLINK_EN}   [ipx::get_bus_interfaces s1_axis -of_objects [ipx::current_core]]
   set_property enablement_dependency {$XBUS_EN}       [ipx::get_bus_interfaces m_axi   -of_objects [ipx::current_core]]
   set_property enablement_dependency {$OCD_EN}        [ipx::get_ports jtag_*           -of_objects [ipx::current_core]]
-  set_property enablement_dependency {$XIP_EN}        [ipx::get_ports xip_*            -of_objects [ipx::current_core]]
   set_property enablement_dependency {$IO_GPIO_EN}    [ipx::get_ports gpio_*           -of_objects [ipx::current_core]]
   set_property enablement_dependency {$IO_UART0_EN}   [ipx::get_ports uart0_*          -of_objects [ipx::current_core]]
   set_property enablement_dependency {$IO_UART1_EN}   [ipx::get_ports uart1_*          -of_objects [ipx::current_core]]
@@ -302,14 +301,6 @@ proc setup_ip_gui {} {
     { DCACHE_BLOCK_SIZE {Block size}       {In bytes (use a power of two)} {$DCACHE_EN} }
   }
 
-  set group [add_group $page {Execute In-Place Module (XIP)}]
-  add_params $group {
-    { XIP_EN               {Enable XIP} }
-    { XIP_CACHE_EN         {Enable XIP cache} {}                              {$XIP_EN} {$XIP_EN ? $XIP_CACHE_EN : false} }
-    { XIP_CACHE_NUM_BLOCKS {Cache blocks}     {}                              {$XIP_CACHE_EN} }
-    { XIP_CACHE_BLOCK_SIZE {Cache block size} {In bytes (use a power of two)} {$XIP_CACHE_EN} }
-  }
-
 
   # **************************************************************
   # GUI Page: Peripherals

diff --git a/rtl/system_integration/neorv32_vivado_ip.vhd b/rtl/system_integration/neorv32_vivado_ip.vhd
@@ -91,11 +91,6 @@ entity neorv32_vivado_ip is
     XBUS_CACHE_EN         : boolean                        := false;
     XBUS_CACHE_NUM_BLOCKS : natural range 1 to 256         := 8;
     XBUS_CACHE_BLOCK_SIZE : natural range 1 to 2**16       := 256;
-    -- Execute in-place module (XIP) --
-    XIP_EN                : boolean                        := false;
-    XIP_CACHE_EN          : boolean                        := false;
-    XIP_CACHE_NUM_BLOCKS  : natural range 1 to 256         := 8;
-    XIP_CACHE_BLOCK_SIZE  : natural range 1 to 2**16       := 256;
     -- Processor peripherals --
     IO_GPIO_EN            : boolean                        := false;
     IO_GPIO_IN_NUM        : natural range 1 to 32          := 1; -- variable-sized ports must be at least 0 downto 0; #974
@@ -199,11 +194,6 @@ entity neorv32_vivado_ip is
     -- ------------------------------------------------------------
     -- Processor IO
     -- ------------------------------------------------------------
-    -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
-    xip_csn_o      : out std_logic;
-    xip_clk_o      : out std_logic;
-    xip_dat_i      : in  std_logic := '0';
-    xip_dat_o      : out std_logic;
     -- GPIO (available if IO_GPIO_IN/OUT_NUM > 0) --
     gpio_o         : out std_logic_vector(IO_GPIO_OUT_NUM-1 downto 0); -- variable-sized ports must be at least 0 downto 0; #974
     gpio_i         : in  std_logic_vector(IO_GPIO_IN_NUM-1 downto 0) := (others => '0'); -- variable-sized ports must be at least 0 downto 0; #974
@@ -311,7 +301,6 @@ architecture neorv32_vivado_ip_rtl of neorv32_vivado_ip is
   signal s0_axis_tdata_aux : std_ulogic_vector(31 downto 0);
   signal s0_axis_tdest_aux : std_ulogic_vector(3 downto 0);
   signal s1_axis_tready_aux, s0_axis_tvalid_aux, s0_axis_tlast_aux : std_ulogic;
-  signal xip_csn_aux, xip_clk_aux, xip_do_aux : std_ulogic;
   signal uart0_txd_aux, uart0_rts_aux, uart1_txd_aux, uart1_rts_aux : std_ulogic;
   signal spi_clk_aux, spi_do_aux : std_ulogic;
   signal spi_csn_aux : std_ulogic_vector(7 downto 0);
@@ -413,11 +402,6 @@ begin
     XBUS_CACHE_EN         => XBUS_CACHE_EN,
     XBUS_CACHE_NUM_BLOCKS => XBUS_CACHE_NUM_BLOCKS,
     XBUS_CACHE_BLOCK_SIZE => XBUS_CACHE_BLOCK_SIZE,
-    -- Execute in-place module --
-    XIP_EN                => XIP_EN,
-    XIP_CACHE_EN          => XIP_CACHE_EN,
-    XIP_CACHE_NUM_BLOCKS  => XIP_CACHE_NUM_BLOCKS,
-    XIP_CACHE_BLOCK_SIZE  => XIP_CACHE_BLOCK_SIZE,
     -- Processor peripherals --
     IO_DISABLE_SYSINFO    => false,
     IO_GPIO_NUM           => num_gpio_c,
@@ -487,11 +471,6 @@ begin
     slink_tx_val_o => s0_axis_tvalid_aux,
     slink_tx_lst_o => s0_axis_tlast_aux,
     slink_tx_rdy_i => std_ulogic(s0_axis_tready),
-    -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
-    xip_csn_o      => xip_csn_aux,
-    xip_clk_o      => xip_clk_aux,
-    xip_dat_i      => std_ulogic(xip_dat_i),
-    xip_dat_o      => xip_do_aux,
     -- GPIO (available if IO_GPIO_NUM > 0) --
     gpio_o         => gpio_o_aux,
     gpio_i         => gpio_i_aux,
@@ -557,10 +536,6 @@ begin
   s0_axis_tvalid <= std_logic(s0_axis_tvalid_aux);
   s0_axis_tlast  <= std_logic(s0_axis_tlast_aux);
 
-  xip_csn_o      <= std_logic(xip_csn_aux);
-  xip_clk_o      <= std_logic(xip_clk_aux);
-  xip_dat_o      <= std_logic(xip_do_aux);
-
   uart0_txd_o    <= std_logic(uart0_txd_aux);
   uart0_rts_o    <= std_logic(uart0_rts_aux);
   uart1_txd_o    <= std_logic(uart1_txd_aux);